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/openbmc/linux/Documentation/devicetree/bindings/gpu/host1x/
H A Dnvidia,tegra234-nvdec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra234-nvdec
32 clock-names:
34 - const: nvdec
[all …]
/openbmc/linux/drivers/gpu/drm/tegra/
H A Driscv.c1 // SPDX-License-Identifier: GPL-2.0-only
32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset) in riscv_writel() argument
34 writel(value, riscv->regs + offset); in riscv_writel()
39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors() local
40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors()
41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors()
47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors()
51 READ_PROP("nvidia,bl-manifest-offset", &bl->manifest_offset); in tegra_drm_riscv_read_descriptors()
52 READ_PROP("nvidia,bl-code-offset", &bl->code_offset); in tegra_drm_riscv_read_descriptors()
53 READ_PROP("nvidia,bl-data-offset", &bl->data_offset); in tegra_drm_riscv_read_descriptors()
[all …]
/openbmc/linux/arch/arm/lib/
H A Dbacktrace-clang.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/lib/backtrace-clang.S
39 * If the call instruction was a bl we can look at the callers branch
45 * Unfortunately due to the stack frame layout we can't dump r0 - r3, but these
52 * optionally saved caller registers (r4 - r10)
53 * optionally saved arguments (r0 - r3)
57 * Functions start with the following code sequence:
60 * stmfd sp!, {r0 - r3} (optional)
69 * The frame for c_backtrace has pointers to the code of dump_stack. This is
82 * show_stack. It points at the instruction directly after the bl dump_stack.
[all …]
/openbmc/linux/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c75 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
229 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", in __8b10b_clock_recovery_delay_us()
230 aux->name, rd_interval); in __8b10b_clock_recovery_delay_us()
241 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", in __8b10b_channel_eq_delay_us()
242 aux->name, rd_interval); in __8b10b_channel_eq_delay_us()
254 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n", in __128b132b_channel_eq_delay_us()
255 aux->name, rd_interval); in __128b132b_channel_eq_delay_us()
277 * - Clock recovery vs. channel equalization
278 * - DPRX vs. LTTPR
279 * - 128b/132b vs. 8b/10b
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/openbmc/u-boot/arch/arm/lib/
H A Dcrt0_64.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * crt0 - C-runtime startup Code for AArch64 U-Boot
13 #include <asm-offsets.h>
18 * This file handles the target-independent stages of the U-Boot
19 * start-up where a C runtime environment is needed. Its entry point
41 * initialized non-const data are still not available.
43 * 4a.For U-Boot proper (not SPL), call relocate_code(). This function
44 * relocates U-Boot from its current location into the relocation
48 * code relocation in SPL.
51 * environment has BSS (initialized to 0), initialized non-const
[all …]
H A Drelocate_64.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * relocate - common relocation function for AArch64 U-Boot
10 #include <asm-offsets.h>
19 * This function relocates the monitor code.
23 stp x29, x30, [sp, #-32]! /* create a stack frame */
27 * Copy u-boot from flash to RAM
29 adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */
30 subs x9, x0, x1 /* x8 <- Run to copy offset */
33 * Don't ldr x1, __image_copy_start here, since if the code is already
39 * CONFIG_SYS_TEXT_BASE, which is stored in _TEXT_BASE, as a non-
[all …]
/openbmc/linux/arch/arm64/kernel/
H A Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level CPU initialisation
6 * Copyright (C) 1994-2002 Russell King
7 * Copyright (C) 2003-2012 ARM Ltd.
21 #include <asm/asm-offsets.h>
27 #include <asm/kernel-pgtable.h>
30 #include <asm/pgtable-hwdef.h>
38 #include "efi-header.S"
46 * ---------------------------
49 * MMU = off, D-cache = off, I-cache = on or off,
[all …]
H A Dftrace.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <asm/debug-monitors.h>
23 int offset; member
29 .offset = offsetof(struct ftrace_regs, field), \
55 if (!strcmp(roff->name, name)) in ftrace_regs_query_register_offset()
56 return roff->offset; in ftrace_regs_query_register_offset()
59 return -EINVAL; in ftrace_regs_query_register_offset()
73 * When using patchable-function-entry without pre-function NOPS, addr in ftrace_call_adjust()
79 * addr+04: NOP // To be patched to BL <caller> in ftrace_call_adjust()
83 * addr-04: BTI C in ftrace_call_adjust()
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/openbmc/linux/arch/powerpc/kernel/
H A Dhead_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Low-level exception handlers and MMU support
16 * This file contains the entry point for the 64-bit kernel along
17 * with some early initialization code common to all 64-bit powerpc
28 #include <asm/head-64.h>
29 #include <asm/asm-offsets.h>
42 #include <asm/ppc-opcode.h>
43 #include <asm/feature-fixups.h>
45 #include <asm/exception-64s.h>
[all …]
H A Dhead_85xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Kernel execution entry point code.
5 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
10 * Low-level exception handers, MMU support, and rewrite.
13 * Copyright (c) 1998-1999 TiVo, Inc.
23 * Copyright 2002-2004 MontaVista Software, Inc.
40 #include <asm/asm-offsets.h>
43 #include <asm/feature-fixups.h>
46 /* As with the other PowerPC ports, it is expected that when code
50 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
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H A Dhead_booke.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 * Macros used for common Book-e exception handling
32 * Note that entries 0-3 are used for the prolog code, and the remaining
36 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
63 lwz r11, TASK_STACK - THREAD(r10); \
101 addi r2, r2, -THREAD
110 bl prepare_transfer_to_handler
139 lwz r1, TASK_STACK - THREAD(r10)
141 ALLOC_STACK_FRAME(r1, THREAD_SIZE - INT_FRAME_SIZE)
148 /* To handle the additional exception priority levels on 40x and Book-E
[all …]
H A Dhead_8xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Low-level exception handlers and MMU support
13 * This file contains low-level support and setup for PowerPC 8xx
30 #include <asm/asm-offsets.h>
32 #include <asm/code-patching-asm.h>
62 * support an ELF compressed (zImage) boot from EPPC-Bug because the
63 * code there loads up some registers before calling us:
66 * r5: initrd_end - unused if r4 is 0
71 * adding more processor specific branches around code I don't need.
[all …]
H A Dmisc_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains miscellaneous low-level functions.
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
21 #include <asm/asm-offsets.h>
27 #include <asm/feature-fixups.h>
184 * The address passed in is the 24 bits register address. This code
251 * the slave code for the next one is at addresses 0 to 100.
254 * paca in the secondary startup code.
261 addi r5,r5,kexec_flag-1b
298 * Invalidate all non-IPROT TLB entries to avoid any TLB conflict.
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2014-2015 Freescale Semiconductor
12 #include <asm/arch-fsl-layerscape/soc.h>
17 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
19 #include <asm/u-boot.h>
21 /* Get GIC offset
63 bl get_gic_offset
64 bl gic_kick_secondary_cpus
88 /* Set Wuo bit for RN-I 20 */
92 bl ccn504_set_aux
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
7 /* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
10 * The processor starts at 0xfff00100 and the code is executed
11 * from flash. The code is organized to be at an other address
16 #include <asm-offsets.h>
26 #include <asm/u-boot.h>
33 * Set up GOT: Global Offset Table
52 * r3 - 1st arg to board_init(): IMMP pointer
53 * r4 - 2nd arg to board_init(): boot flag
56 .long 0x27051956 /* U-Boot Magic Number */
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
8 /* U-Boot - Startup Code for PowerPC based Embedded Boards
11 * The processor starts at 0x00000100 and the code is executed
12 * from flash. The code is organized to be at an other address
23 #include <asm-offsets.h>
33 #include <asm/u-boot.h>
41 * Set up GOT: Global Offset Table
60 * r3 - 1st arg to board_init(): IMMP pointer
61 * r4 - 2nd arg to board_init(): boot flag
64 .long 0x27051956 /* U-Boot Magic Number */
[all …]
/openbmc/linux/fs/nfs/blocklayout/
H A Dblocklayout.c54 switch (be->be_state) { in is_hole()
58 return be->be_tag ? false : true; in is_hole()
79 rv->data = data; in alloc_parallel()
80 kref_init(&rv->refcnt); in alloc_parallel()
87 kref_get(&p->refcnt); in get_parallel()
95 p->pnfs_callback(p->data); in destroy_parallel()
101 kref_put(&p->refcnt, destroy_parallel); in put_parallel()
108 get_parallel(bio->bi_private); in bl_submit_bio()
111 bio->bi_iter.bi_size, in bl_submit_bio()
112 (unsigned long long)bio->bi_iter.bi_sector); in bl_submit_bio()
[all …]
/openbmc/linux/arch/arm/boot/compressed/
H A Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2002 Russell King
12 #include "efi-header.S"
20 AR_CLASS( .arch armv7-a )
21 M_CLASS( .arch armv7-m )
26 * Note that these macros must not contain any code which is not
82 bl putc
88 bl phex
101 kputc #'-'
105 kputc #'-'
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dnonsec_virt.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * code for switching cores into non-secure state and into HYP mode
12 #include <asm/proc-armv/ptrace.h>
39 * U-Boot calls this "software interrupt" in start.S
41 * to non-secure state.
52 bl psci_stack_setup
56 bl psci_arch_init
104 movs pc, lr @ ERET to non-secure
125 add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset
131 movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
[all …]
/openbmc/linux/arch/loongarch/kernel/
H A Dhead.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
18 #include "efi-header.S"
23 .word MZ_MAGIC /* "MZ", MS-DOS header */
27 .quad PHYS_LINK_KADDR /* Kernel image load offset from start of RAM */
30 .long pe_header - _head /* Offset to the PE header */
64 la.pcrel t1, __bss_stop - LONGSIZE
84 PTR_LI sp, (_THREAD_SIZE - PT_SIZE)
90 bl relocate_kernel
94 PTR_LI sp, (_THREAD_SIZE - PT_SIZE)
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
10 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
13 #include <asm-offsets.h>
25 #include <asm/u-boot.h>
51 * Set up GOT: Global Offset Table
86 * Magic number and version string - put it after the HRCW since it
89 .long 0x27051956 /* U-Boot Magic Number */
139 * vector at offset 0x100 relative to the base set by MSR[IP]. If
148 * so that we eventually end up executing the code below when the
170 bl 1f
[all …]
/openbmc/qemu/hw/block/
H A Dblock.c2 * Common code for block device models
7 * later. See the COPYING file in the top-level directory.
11 #include "block/block_int-common.h"
13 #include "sysemu/block-backend.h"
16 #include "qapi/qapi-types-block.h"
19 * Read the non-zeroes parts of @blk into @buf
22 * the non-zeroes block into @buf.
24 * Return 0 on success, non-zero on error.
29 int64_t bytes, offset = 0; in blk_pread_nonzeroes() local
33 bytes = MIN(size - offset, BDRV_REQUEST_MAX_BYTES); in blk_pread_nonzeroes()
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dentry-common.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/entry-common.S
14 #include <asm/unistd-oabi.h>
19 #include "entry-header.S"
37 * have tracing, context tracking and rseq debug disabled - the overheads
45 ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing
49 restore_user_regs fast = 1, offset = S_OFF
72 bl do_rseq_syscall
75 ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing
81 /* Slower path - fall through to work_pending */
[all …]
H A Dhead-common.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-common.S
5 * Copyright (C) 1994-2002 Russell King
18 #define OF_DT_MAGIC 0xedfe0dd0 /* 0xd00dfeed in big-endian */
68 * The following fragment of code is executed with the MMU on in MMU mode,
71 * r0 = cp#15 control register (exc_ret for M-class)
90 bl __inflate_kernel_data @ decompress .data to RAM
98 bl __memcpy @ copy .data to RAM
106 bl __memset @ clear .bss
118 bl kasan_early_init
[all …]
/openbmc/qemu/block/
H A Dio.c27 #include "sysemu/block-backend.h"
28 #include "block/aio-wait.h"
33 #include "block/dirty-bitmap.h"
34 #include "block/write-threshold.h"
38 #include "qemu/error-report.h"
39 #include "qemu/main-loop.h"
42 /* Maximum bounce buffer for copy-on-read and write zeroes, in bytes */
49 int64_t offset, int64_t bytes, BdrvRequestFlags flags);
58 QLIST_FOREACH_SAFE(c, &bs->parents, next_parent, next) { in bdrv_parent_drained_begin()
70 assert(c->quiesced_parent); in bdrv_parent_drained_end_single()
[all …]

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