Home
last modified time | relevance | path

Searched full:bit1 (Results 1 – 25 of 240) sorted by relevance

12345678910

/openbmc/linux/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h50 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x…
58 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable fallin…
59 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 …
60 …{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1…
62 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR …
71 …{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1…
73 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 …
74 …SK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x…
89 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power s…
96 …WR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power s…
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h29 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
57 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
66 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
69 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
170 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
173 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
253 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
259 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
288 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
294 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
[all …]
/openbmc/linux/include/linux/
H A Dmman.h130 * (x & bit1) ? bit2 : 0
132 * ("bit1" and "bit2" must be single bits)
134 #define _calc_vm_trans(x, bit1, bit2) \ argument
135 ((!(bit1) || !(bit2)) ? 0 : \
136 ((bit1) <= (bit2) ? ((x) & (bit1)) * ((bit2) / (bit1)) \
137 : ((x) & (bit1)) / ((bit1) / (bit2))))
/openbmc/linux/Documentation/driver-api/mtd/
H A Dnand_ecc.rst45 byte 0: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp4 ... rp14
46 byte 1: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp2 rp4 ... rp14
47 byte 2: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp3 rp4 ... rp14
48 byte 3: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp3 rp4 ... rp14
49 byte 4: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp5 ... rp14
51 byte 254: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp3 rp5 ... rp15
52 byte 255: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp3 rp5 ... rp15
67 Similarly cp1 is the sum of all bit1, bit3, bit5 and bit7.
69 - cp2 is the parity over bit0, bit1, bit4 and bit5
71 - cp4 is the parity over bit0, bit1, bit2 and bit3.
[all …]
/openbmc/linux/drivers/video/fbdev/via/
H A Ddvi.c45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
325 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); in dvi_patch_skew_dvp0()
335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
346 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); in dvi_patch_skew_dvp0()
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_hw.h72 #define RCR_APM BIT1
99 #define SCR_RxUseDK BIT1
121 #define IMR_VODOK BIT1
139 #define ACM_HW_BEQ_EN BIT1
182 #define RRSR_2M BIT1
/openbmc/linux/drivers/video/fbdev/
H A Dwm8505fb_regs.h17 * BIT1 GOVRH_VGA_YUV2RGB_ENABLE
26 * BIT1 GOVRH_DVO_YUV422
50 * BIT1 GOVRH_DVO_SYNC_POLAR
/openbmc/libpldm/include/libpldm/
H A Dpldm_types.h11 uint8_t bit1 : 1; member
38 uint8_t bit1 : 1; member
60 uint8_t bit1 : 1; member
98 uint8_t bit1 : 1; member
/openbmc/linux/Documentation/input/devices/
H A Dsentelic.rst38 Bit1 => Right Button, 1 is pressed, 0 is not pressed.
70 Bit1 => Right Button, 1 is pressed, 0 is not pressed.
75 Bit1 => the Vertical scrolling movement upward.
115 Bit1 => Right Button, 1 is pressed, 0 is not pressed.
119 Byte 4: Bit1~Bit0 => Y coordinate (xpos[1:0])
139 Bit1 => Right Button, 1 is pressed, 0 is not pressed.
170 Bit1 => 0
174 Byte 4: Bit1~Bit0 => Y coordinate (xpos[1:0])
195 Bit1 => 1
199 Byte 4: Bit1~Bit0 => Y coordinate (xpos[1:0])
[all …]
/openbmc/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg65 # bit1-0: 00, Cs0width=x8
100 # bit1: 0, DDR drive strenght normal
124 # bit1: 0, Write Protect disabled
138 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/libcper/include/libcper/
H A DCper.h44 #define EFI_ERROR_RECORD_HEADER_TIME_STAMP_VALID BIT1
179 #define EFI_ERROR_SECTION_FRU_STRING_VALID BIT1
186 #define EFI_ERROR_SECTION_FLAGS_CONTAINMENT_WARNING BIT1
288 #define EFI_GENERIC_ERROR_PROC_ISA_VALID BIT1
345 #define EFI_GENERIC_ERROR_PROC_FLAGS_PRECISE_IP BIT1
412 #define EFI_IA32_X64_PROCESSOR_ERROR_CPU_ID_INFO_VALID BIT1
429 #define EFI_CACHE_CHECK_OPERATION_VALID BIT1
482 #define EFI_TLB_CHECK_OPERATION_VALID BIT1
533 #define EFI_BUS_CHECK_OPERATION_VALID BIT1
608 #define EFI_MS_CHECK_CONTEXT_CORRUPT_VALID BIT1
[all …]
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg70 # bit1-0: 0, Cs0width=x8
104 # bit1: 0, DRAM drive strength normal
144 # bit1: 0, Write Protect disabled
152 # bit1: 0, Write Protect disabled
169 # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg60 # bit1-0: 00, Cs0width=x8
94 # bit1: 1, DDR drive strenght reduced
122 # bit1: 0, Write Protect disabled
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
H A Dkwbimage-is2.cfg60 # bit1-0: 00, Cs0width=x8
94 # bit1: 1, DDR drive strenght reduced
122 # bit1: 0, Write Protect disabled
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
H A Dkwbimage-ns2l.cfg60 # bit1-0: 00, Cs0width=x8
94 # bit1: 1, DDR drive strenght reduced
122 # bit1: 0, Write Protect disabled
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg63 # bit1-0: 00, Cs0width=x8
97 # bit1: 0, DDR drive strenght normal
125 # bit1: 0, Write Protect disabled
138 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/tools/
H A Dvybridimage.c43 uint8_t bit1 = (byte & (1 << 1)) ? 1 : 0; in vybridimage_sw_ecc() local
53 res |= ((bit7 ^ bit5 ^ bit4 ^ bit2 ^ bit1) << 1); in vybridimage_sw_ecc()
54 res |= ((bit7 ^ bit6 ^ bit5 ^ bit1 ^ bit0) << 2); in vybridimage_sw_ecc()
56 res |= ((bit6 ^ bit4 ^ bit3 ^ bit2 ^ bit1 ^ bit0) << 4); in vybridimage_sw_ecc()
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg64 # bit1-0: 00, Cs0width=x8
98 # bit1: 0, DDR drive strenght normal
126 # bit1: 0, Write Protect disabled
144 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/iomega/iconnect/
H A Dkwbimage.cfg60 # bit1-0: 00, Cs0width (x8)
94 # bit1: 0, DDR drive strenght normal
122 # bit1: 0x0, Write Protect disabled
140 # bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/Synology/ds109/
H A Dkwbimage.cfg64 # bit1-0: 01, Cs0width=x8
98 # bit1: 0, DDR drive strenght normal
126 # bit1: 0, Write Protect disabled
141 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg66 # bit1-0: 00, Cs0width=x8
100 # bit1: 0, DDR drive strenght normal
128 # bit1: 0, Write Protect disabled
141 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg60 # bit1-0: 01, Cs0width=x16
94 # bit1: 1, DDR drive strenght reduced
122 # bit1: 0, Write Protect disabled
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg61 # bit1-0: 01, Cs0width=x8
95 # bit1: 0, DDR drive strenght normal
123 # bit1: 0, Write Protect disabled
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg60 # bit1-0: 00, Cs0width=x8
94 # bit1: 0, DDR drive strenght normal
122 # bit1: 0, Write Protect disabled
135 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/Marvell/guruplug/
H A Dkwbimage.cfg60 # bit1-0: 01, Cs0width=x8
94 # bit1: 0, DDR drive strenght normal
122 # bit1: 0, Write Protect disabled
135 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above

12345678910