Searched full:axi_clkgen (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/clk/ |
| H A D | clk-axi-clkgen.c | 57 struct axi_clkgen { struct
232 static void axi_clkgen_write(struct axi_clkgen *axi_clkgen, in axi_clkgen_write() argument
235 writel(val, axi_clkgen->base + reg); in axi_clkgen_write()
238 static void axi_clkgen_read(struct axi_clkgen *axi_clkgen, in axi_clkgen_read() argument
241 *val = readl(axi_clkgen->base + reg); in axi_clkgen_read()
244 static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen) in axi_clkgen_wait_non_busy() argument
250 axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val); in axi_clkgen_wait_non_busy()
259 static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, in axi_clkgen_mmcm_read() argument
265 ret = axi_clkgen_wait_non_busy(axi_clkgen); in axi_clkgen_mmcm_read()
272 axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val); in axi_clkgen_mmcm_read()
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | adi,axi-clkgen.yaml | 14 The axi_clkgen IP core is a software programmable clock generator,
17 Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen
|