Searched +full:ax45mp +full:- +full:cache (Results 1 – 7 of 7) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Andestech AX45MP L2 Cache Controller11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>14 A level-2 cache (L2C) is used to improve the system performance by providing15 a large amount of cache line entries and reasonable access delays. The L2C16 is shared between cores, and a non-inclusive non-exclusive policy is used.23 - andestech,ax45mp-cache[all …]
1 # SPDX-License-Identifier: GPL-2.02 menu "Cache Drivers"5 bool "Andes Technology AX45MP L2 Cache controller"9 Support for the L2 cache controller on Andes Technology AX45MP platforms.
1 // SPDX-License-Identifier: GPL-2.03 * non-coherent cache functions for Andes AX45MP10 #include <linux/dma-direction.h>14 #include <asm/dma-noncoherent.h>16 /* L2 cache registers */23 /* D-cache operation */24 #define AX45MP_CCTL_L1D_VA_INVAL 0 /* Invalidate an L1 cache entry */25 #define AX45MP_CCTL_L1D_VA_WB 1 /* Write-back an L1 cache entry */33 /* L2 cache operation */34 #define AX45MP_CCTL_L2_PA_INVAL 0x8 /* Invalidate an L2 cache entry */[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/interrupt-controller/irq.h>16 #address-cells = <1>;17 #size-cells = <0>;18 timebase-frequency = <12000000>;21 compatible = "andestech,ax45mp", "riscv";23 #cooling-cells = <2>;27 mmu-type = "riscv,sv39";28 i-cache-size = <0x8000>;29 i-cache-line-size = <0x40>;[all …]
4 bool "Andes AX45MP errata"14 bool "Apply Andes cache management errata"19 This will apply the cache management errata to handle the20 non-standard handling on non-coherent operations on Andes cores.35 bool "Apply SiFive errata CIP-453"39 This will apply the SiFive CIP-453 errata to add sign extension46 bool "Apply SiFive errata CIP-1200"50 This will apply the SiFive CIP-1200 errata to repalce all57 bool "T-HEAD errata"60 All T-HEAD errata Kconfig depend on this Kconfig. Disabling[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: RISC-V CPUs10 - Paul Walmsley <paul.walmsley@sifive.com>11 - Palmer Dabbelt <palmer@sifive.com>12 - Conor Dooley <conor@kernel.org>15 This document uses some terminology common to the RISC-V community19 mandated by the RISC-V ISA: a PC and some registers. This27 - $ref: /schemas/cpu.yaml#[all …]
1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'3 2024-12-2[all...]