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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]
H A Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-xp-mv78460.dtsi6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
50 #include "armada-xp.dtsi"
54 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
64 #address-cells = <1>;
65 #size-cells = <0>;
66 enable-method = "marvell,armada-xp-smp";
70 compatible = "marvell,sheeva-v7";
73 clock-latency = <1000000>;
78 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-xp-mv78260.dtsi6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
50 #include "armada-xp.dtsi"
54 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
63 #address-cells = <1>;
64 #size-cells = <0>;
65 enable-method = "marvell,armada-xp-smp";
69 compatible = "marvell,sheeva-v7";
72 clock-latency = <1000000>;
77 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-385.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
30 compatible = "arm,cortex-a9";
37 compatible = "marvell,armada-370-pcie";
[all …]
H A Darmada-xp-mv78230.dtsi6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
50 #include "armada-xp.dtsi"
54 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
62 #address-cells = <1>;
63 #size-cells = <0>;
64 enable-method = "marvell,armada-xp-smp";
68 compatible = "marvell,sheeva-v7";
71 clock-latency = <1000000>;
76 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-380.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
31 internal-regs {
33 compatible = "marvell,mv88f6810-pinctrl";
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-xp-mv78260.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-385.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
30 compatible = "arm,cortex-a9";
37 compatible = "marvell,armada-370-pcie";
[all …]
H A Darmada-xp-mv78230.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-380.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
31 internal-regs {
33 compatible = "marvell,mv88f6810-pinctrl";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcavium-mdio.txt4 - compatible: One of:
6 "cavium,octeon-3860-mdio": Compatibility with all cn3XXX, cn5XXX
9 "cavium,thunder-8890-mdio": Compatibility with all cn8XXX SOCs.
11 - reg: The base address of the MDIO bus controller register bank.
13 - #address-cells: Must be <1>.
15 - #size-cells: Must be <0>. MDIO addresses have no size component.
21 compatible = "cavium,octeon-3860-mdio";
22 #address-cells = <1>;
23 #size-cells = <0>;
26 ethernet-phy@0 {
[all …]
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-driver-intel-m10-bmc1 What: /sys/bus/.../drivers/intel-m10-bmc/.../bmc_version
9 What: /sys/bus/.../drivers/intel-m10-bmc/.../bmcfw_version
17 What: /sys/bus/.../drivers/intel-m10-bmc/.../mac_address
22 of sequential MAC addresses assigned to the board
28 What: /sys/bus/.../drivers/intel-m10-bmc/.../mac_count
33 addresses assigned to the board managed by the Intel
/openbmc/linux/Documentation/security/
H A DSCTP.rst1 .. SPDX-License-Identifier: GPL-2.0
11 --------------
26 Passes the ``@asoc`` and ``@chunk->skb`` of the association INIT packet to the
30 @asoc - pointer to sctp association structure.
31 @skb - pointer to skbuff of association packet.
36 Passes one or more ipv4/ipv6 addresses to the security module for validation
42 @sk - Pointer to sock structure.
43 @optname - Name of the option to validate.
44 @address - One or more ipv4 / ipv6 addresses.
45 @addrlen - The total length of address(s). This is calculated on each
[all …]
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-protocols/zeroconf/
H A Dzeroconf_0.9.bb1 SUMMARY = "IPv4 link-local address allocator"
3 link-local addresses. IPv4 link-local addresses are useful when setting \
4 up ad-hoc networking between devices without the involvement of a either \
6 These addresses are allocated from the 169.254.0.0/16 address range and \
8 Addresses are assigned randomly by each host and, in case of collision, \
11 LICENSE = "GPL-2.0-or-later"
17 SRC_URI = "http://www.progsoc.org/~wildfire/zeroconf/download/${BPN}-${PV}.tar.gz \
19 file://makefile-add-ldflags.patch \
20 file://zeroconf-default \
21 file://debian-zeroconf \
[all …]
/openbmc/linux/include/linux/
H A Detherdevice.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
69 /* Reserved Ethernet Addresses per IEEE 802.1Q */
75 * is_link_local_ether_addr - Determine if given Ethernet address is link-local
76 * @addr: Pointer to a six-byte array containing the Ethernet address
98 * is_zero_ether_addr - Determine if give Ethernet address is all zeros.
99 * @addr: Pointer to a six-byte array containing the Ethernet address
117 * is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
118 * @addr: Pointer to a six-byte array containing the Ethernet address
131 return 0x01 & (a >> ((sizeof(a) * 8) - 8)); in is_multicast_ether_addr()
151 * is_local_ether_addr - Determine if the Ethernet address is locally-assigned one (IEEE 802).
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/
H A DIPAddresses.v1_1_5.json3 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
4 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
14 …ddress is currently within its valid lifetime but is now outside its RFC4862-defined preferred lif…
16 …"Preferred": "This address is currently within both its RFC4862-defined valid and preferred lifeti…
24 "longDescription": "This type shall describe an IPv4 address assigned to an interface.",
26 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
42 …hall contain an IPv4 address assigned to this interface. If DHCPv4 is enabled on the interface, t…
43 "pattern": "^(?:[0-9]{1,3}\\.){3}[0-9]{1,3}$",
65 … read-only. If multiple IPv4 addresses are present on the same interface, only a single default g…
66 "pattern": "^(?:[0-9]{1,3}\\.){3}[0-9]{1,3}$",
[all …]
H A DEthernetInterface.v1_12_3.json4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
58 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
97 … "description": "An indication of whether this interface uses DHCP v4-supplied DNS servers.",
98 …scription": "This property shall indicate whether the interface uses DHCP v4-supplied DNS servers.…
107 … "description": "An indication of whether this interface uses a DHCP v4-supplied domain name.",
108 …ription": "This property shall indicate whether the interface uses a DHCP v4-supplied domain name.…
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/
H A DIPAddresses.v1_1_5.json3 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
4 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
14 …ddress is currently within its valid lifetime but is now outside its RFC4862-defined preferred lif…
16 …"Preferred": "This address is currently within both its RFC4862-defined valid and preferred lifeti…
24 "longDescription": "This type shall describe an IPv4 address assigned to an interface.",
26 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
42 …hall contain an IPv4 address assigned to this interface. If DHCPv4 is enabled on the interface, t…
43 "pattern": "^(?:[0-9]{1,3}\\.){3}[0-9]{1,3}$",
65 … read-only. If multiple IPv4 addresses are present on the same interface, only a single default g…
66 "pattern": "^(?:[0-9]{1,3}\\.){3}[0-9]{1,3}$",
[all …]
H A DEthernetInterface.v1_12_3.json4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
58 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
97 … "description": "An indication of whether this interface uses DHCP v4-supplied DNS servers.",
98 …scription": "This property shall indicate whether the interface uses DHCP v4-supplied DNS servers.…
107 … "description": "An indication of whether this interface uses a DHCP v4-supplied domain name.",
108 …ription": "This property shall indicate whether the interface uses a DHCP v4-supplied domain name.…
[all …]
/openbmc/linux/Documentation/powerpc/
H A Dpci_iov_resource_on_powernv.rst57 - For DMA we then provide an entire address space for each PE that can
63 - For MSIs, we have two windows in the address space (one at the top of
64 the 32-bit space and one much higher) which, via a combination of the
70 - Error messages just use the RTT.
81 - The M32 window:
87 32-bit PCIe accesses. We configure that window at boot from FW and
97 to be assigned to PEs on a segment granularity. For a 2GB window,
101 SR-IOV). We basically use the trick of forcing the bridge MMIO windows
103 can be assigned to a PE.
110 - The M64 windows:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-atr.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-atr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
22 i2c-alias-pool:
23 $ref: /schemas/types.yaml#/definitions/uint32-array
25 I2C alias pool is a pool of I2C addresses on the main I2C bus that can be
27 addresses must be available, not used by any other peripheral. Each
28 remote peripheral is assigned an alias from the pool, and transactions to
/openbmc/linux/include/linux/mfd/
H A Daltera-a10sr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
19 /* Write registers are always on even addresses */
21 /* Odd registers are always on odd addresses */
28 * by 2 because the reads are at odd addresses.
39 #define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */
41 #define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */
45 #define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Input only */
65 * struct altr_a10sr - Altera Max5 MFD device private data structure
67 * @regmap: the regmap assigned to the parent device.
/openbmc/linux/Documentation/arch/x86/
H A Dsva.rst1 .. SPDX-License-Identifier: GPL-2.0
11 same virtual addresses avoiding the need for software to translate virtual
12 addresses to physical addresses. SVA is what PCIe calls Shared Virtual
15 In addition to the convenience of using application virtual addresses
19 application page-faults. For more information please refer to the PCIe
24 to cache translations for virtual addresses. The IOMMU driver uses the
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
52 performed, virtual addresses of all parameters, virtual address of a completion
[all …]

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