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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Darm-pl08x.yaml59 lli-bus-interface-ahb2:
67 mem-bus-interface-ahb2:
115 lli-bus-interface-ahb2;
116 mem-bus-interface-ahb2;
135 lli-bus-interface-ahb2;
136 mem-bus-interface-ahb2;
H A Dlpc1850-dmamux.txt30 lli-bus-interface-ahb2;
32 mem-bus-interface-ahb2;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-ahb-clk.yaml23 - allwinner,sun8i-h3-ahb2-clk
73 const: allwinner,sun8i-h3-ahb2-clk
102 compatible = "allwinner,sun8i-h3-ahb2-clk";
105 clock-output-names = "ahb2";
H A Dallwinner,sun8i-h3-bus-gates-clk.yaml61 clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
62 clock-names = "ahb1", "ahb2", "apb1", "apb2";
H A Dst,stm32-rcc.txt62 /* Gated clock, AHB2 bit 4 (CRYP) */
/openbmc/u-boot/include/
H A Dstm32_rcc.h65 u32 ahb2rstr; /* RCC AHB2 peripheral reset */
72 u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
79 u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
/openbmc/linux/drivers/clk/sunxi/
H A Dclk-sun8i-bus-gates.c22 static const char * const names[] = { "ahb1", "ahb2", "apb1", "apb2" }; in sun8i_h3_bus_gates_init()
23 enum { AHB1, AHB2, APB1, APB2, PARENT_MAX } clk_parent; in sun8i_h3_bus_gates_init() enumerator
66 clk_parent = AHB2; in sun8i_h3_bus_gates_init()
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun50i-h6.c237 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
246 "psi-ahb1-ahb2",
281 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
294 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
304 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
316 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
326 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
336 static SUNXI_CCU_GATE(bus_emce_clk, "bus-emce", "psi-ahb1-ahb2",
346 static SUNXI_CCU_GATE(bus_vp9_clk, "bus-vp9", "psi-ahb1-ahb2",
349 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
[all …]
H A Dccu-sun50i-a100.c275 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
283 "psi-ahb1-ahb2",
320 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
334 static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
344 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
355 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
365 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
368 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
371 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2",
374 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2",
[all …]
H A Dccu-sun50i-h616.c248 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
257 "psi-ahb1-ahb2",
292 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
303 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
312 static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
326 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
337 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
347 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
350 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
353 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
[all …]
H A Dccu-sun9i-a80.c294 .hw.init = CLK_HW_INIT_PARENTS("ahb2",
760 /* AHB2 bus gates */
761 static SUNXI_CCU_GATE(bus_lcd0_clk, "bus-lcd0", "ahb2",
763 static SUNXI_CCU_GATE(bus_lcd1_clk, "bus-lcd1", "ahb2",
765 static SUNXI_CCU_GATE(bus_edp_clk, "bus-edp", "ahb2",
767 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb2",
769 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb2",
771 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb2",
773 static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb2",
775 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb2",
[all …]
H A Dccu-sun8i-h3.c210 .hw.init = CLK_HW_INIT_PARENTS("ahb2",
231 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
245 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
247 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb2",
249 static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb2",
253 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
255 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb2",
257 static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb2",
H A Dccu-sun8i-a83t.c288 .hw.init = CLK_HW_INIT_PARENTS("ahb2",
311 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
321 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb2",
323 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
325 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb2",
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun9i.h31 u32 ahb2_cfg; /* 0x68 ahb2 clock configuration */
85 u32 ahb_gate2; /* 0x588 AHB2 Gating Register */
92 u32 ahb_reset2_cfg; /* 0x5a8 AHB2 Software Reset Register */
H A Dcpu_sun9i.h57 /* AHB2 Module */
/openbmc/linux/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h37 /* AHB2 */
H A Dstm32f7-rcc.h38 /* AHB2 */
H A Dstm32h7-rcc.h30 /* AHB2 */
/openbmc/u-boot/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h37 /* AHB2 */
H A Dstm32f7-rcc.h37 /* AHB2 */
H A Dstm32h7-rcc.h31 /* AHB2 */
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32-rcc.txt55 /* Gated clock, AHB2 bit 4 (CRYP) */
/openbmc/u-boot/arch/mips/mach-jz47xx/include/mach/
H A Djz4780.h15 /* AHB2 BUS Devices */
/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi863 lli-bus-interface-ahb2;
864 mem-bus-interface-ahb2;
877 lli-bus-interface-ahb2;
878 mem-bus-interface-ahb2;
/openbmc/qemu/include/hw/misc/
H A Dstm32l4x5_rcc.h83 /* - AHB2 */

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