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/openbmc/webui-vue/docs/guide/unit-testing/
H A Dreadme.md5 require consistent updating when refactoring code are likely tightly coupled to
13 > -- Ed Yerburgh, Testing Vue Applications (New York: Manning
21 - @vue/cli-plugin-unit-jest
22 - @vue/test-utils
26 - Create the test files in the /tests/unit directory
27 - The naming convention is to replicate the folder and component name
31 - The AppHeader.vue single-file component's (SFC) spec file is named
33 - Create a global component like `PageSection.vue` in the `/tests/global`
35 - Create a mixin like BVToastMixin in the `/tests/mixins` directory with the
64 `npm run test:unit -- --watch` and verify each snapshot.
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/openbmc/linux/arch/csky/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
39 select ARCH_WANT_FRAME_POINTERS if !CPU_CK610 && $(cc-option,-mbacktrace)
151 In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
186 # VA_BITS - PAGE_SHIFT - 3
236 prompt "C-SKY PMU type"
266 bool "Tightly-Coupled/Sram Memory"
269 The implementation are not only used by TCM (Tightly-Coupled Memory)
272 re-used directly.
316 bool "Symmetric Multi-Processing (SMP) support for C-SKY"
321 int "Maximum number of CPUs (2-32)"
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/openbmc/linux/Documentation/arch/arm/
H A Dtcm.rst2 ARM TCM (Tightly-Coupled Memory) handling in Linux
7 Some ARM SoCs have a so-called TCM (Tightly-Coupled Memory).
8 This is usually just a few (4-64) KiB of RAM inside the ARM
12 Harvard-architecture, so there is an ITCM (instruction TCM)
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
52 - FIQ and other interrupt handlers that need deterministic
55 - Idle loops where all external RAM is set to self-refresh
56 retention mode, so only on-chip RAM is accessible by
60 - Other operations which implies shutting off or reconfiguring
66 - Define the physical address and size of ITCM and DTCM.
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,nvic.txt3 The NVIC provides an interrupt controller that is tightly coupled to
4 Cortex-M based processor cores. The NVIC implemented on different SoCs
9 - compatible : should be one of:
10 "arm,v6m-nvic"
11 "arm,v7m-nvic"
12 "arm,v8m-nvic"
13 - interrupt-controller : Identifies the node as an interrupt controller
14 - #interrupt-cells : Specifies the number of cells needed to encode an
21 - reg : Specifies base physical address(s) and size of the NVIC registers.
24 - arm,num-irq-priority-bits: The number of priority bits implemented by the
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/openbmc/linux/Documentation/driver-api/hte/
H A Dtegra-hte.rst1 .. SPDX-License-Identifier: GPL-2.0+
7 -----------
15 --------
19 instance supports timestamping GPIOs in real time as it is tightly coupled with
31 specified during IOCTL calls. Refer to ``tools/gpio/gpio-event-mon.c``, which
35 -----------------------------------------
40 one-to-one mapping with IRQ GTE provider, consumers can simply specify the IRQ
45 ``drivers/hte/hte-tegra194.c``. The test driver
46 ``drivers/hte/hte-tegra194-test.c`` demonstrates HTE API usage for both IRQ
/openbmc/phosphor-post-code-manager/
H A DREADME.md1 # phosphor-post-code-manager
3 This phosphor-post-code-manager repository provides an infrastructure to persist
9 To build phosphor-post-code-manager package , do the following steps:
13 ninja -C <build directory>
20 [template version](https://github.com/openbmc/docs/blob/master/designs/multi-host-postcode.md)
22 [dbus interfaces & methods](https://github.com/openbmc/phosphor-dbus-interfaces/blob/master/yaml/xy…
27 This repository is tightly coupled with
28 [phosphor-host-postd](https://github.com/openbmc/phosphor-host-postd) OpenBMC
32 phosphor-post-code-manager is architected to look for the property changed
34 [Value](https://github.com/openbmc/phosphor-dbus-interfaces/blob/master/yaml/xyz/openbmc_project/St…
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/openbmc/linux/Documentation/sound/soc/
H A Doverview.rst6 provide better ALSA support for embedded system-on-chip processors (e.g.
9 had some limitations:-
11 * Codec drivers were often tightly coupled to the underlying SoC
12 CPU. This is not ideal and leads to code duplication - for example,
18 machine specific code to re-route audio, enable amps, etc., after such an
31 features :-
54 multiple re-usable component drivers :-
/openbmc/openbmc-test-automation/redfish/extended/
H A Dtest_basic_ci.robot18 ${ERROR_REGEX} SEGV|core-dump|FAILURE|Failed to start|Found ordering cycle
32 # Application services running on the BMC are not tightly coupled.
36 # root@witherspoon:~# systemctl list-jobs --no-pager | cat
42 # root@witherspoon:~# systemctl list-jobs --no-pager | cat
47 ... systemctl list-jobs --no-pager | cat
63 …Check For Regex In Journald ${ERROR_REGEX} error_check=${0} boot=-b filter_string=${SKIP_ERROR}
99 ... journalctl --no-pager | egrep '${STANDBY_REGEX}' | tail -1
/openbmc/linux/drivers/cpuidle/
H A Dcoupled.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * coupled.c - helper functions to enter the same idle state on multiple cpus
21 * DOC: Coupled cpuidle states
30 * WFI), and one or more "coupled" power states that affect blocks
32 * sometimes the whole SoC). Entering a coupled power state must
33 * be tightly controlled on both cpus.
36 * WFI state until all cpus are ready to enter a coupled state, at
37 * which point the coupled state function will be called on all
46 * ready counter matches the number of online coupled cpus. If any
50 * requested_state stores the deepest coupled idle state each cpu
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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H A Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
27 Each Dual-Core R5F sub-system is represented as a single DTS node
40 - ti,am62-r5fss
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/openbmc/linux/arch/arm/include/asm/
H A Dcp15.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #define CR_P (1 << 4) /* 32-bit exception handler */
15 #define CR_D (1 << 5) /* 32-bit data address range */
55 extern unsigned long cr_alignment; /* defined in entry-armv.S */
107 * cr_alignment is tightly coupled to cp15 (at least in the minds of the
109 * read-only) is fine for most cases and saves quite some #ifdeffery.
/openbmc/linux/drivers/media/platform/mediatek/vpu/
H A Dmtk_vpu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
25 * enum ipi_id - the id of inter-processor interrupt
67 * enum rst_id - reset id to register reset function for VPU watchdog timeout
82 * vpu_ipi_register - register an ipi function
98 * vpu_ipi_send - send data from AP to vpu.
105 * This function is thread-safe. When this function returns,
117 * vpu_get_plat_device - get VPU's platform device
128 * vpu_wdt_reg_handler - register a VPU watchdog handler
146 * vpu_get_vdec_hw_capa - get video decoder hardware capability
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H A Dmtk_vpu.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
18 #include <linux/dma-mapping.h>
33 /* maximum program/data TCM (Tightly-Coupled Memory) size */
68 /* vpu inter-processor communication interrupt */
74 * enum vpu_fw_type - VPU firmware type
86 * struct vpu_mem - VPU extended program/data memory information
98 * struct vpu_regs - VPU TCM and configuration registers
100 * @tcm: the register for VPU Tightly-Coupled Memory
111 * struct vpu_wdt_handler - VPU watchdog reset handler
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/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62a-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "pinctrl-single";
12 #pinctrl-cells = <1>;
13 pinctrl-single,register-width = <32>;
14 pinctrl-single,function-mask = <0xffffffff>;
24 compatible = "ti,am654-timer";
27 clock-names = "fck";
28 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
29 ti,timer-pwm;
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H A Dk3-am62-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "pinctrl-single";
12 #pinctrl-cells = <1>;
13 pinctrl-single,register-width = <32>;
14 pinctrl-single,function-mask = <0xffffffff>;
18 compatible = "ti,j721e-esm";
20 ti,esm-pins = <0>, <1>, <2>, <85>;
29 compatible = "ti,am654-timer";
32 clock-names = "fck";
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/openbmc/linux/drivers/bus/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
61 AXI3-bus is the main communication bus connecting all high-speed
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
114 cores. This bus is for per-CPU tightly coupled devices such as the
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/openbmc/linux/drivers/power/supply/
H A Dab8500_bmdata.c1 // SPDX-License-Identifier: GPL-2.0
6 #include "ab8500-bm.h"
57 { .temp = -10, .resistance = 158 /* 445 mOhm */ },
58 { .temp = -20, .resistance = 198 /* 595 mOhm */ },
144 struct device *dev = &psy->dev; in ab8500_bm_of_probe()
147 ret = power_supply_get_battery_info(psy, &bm->bi); in ab8500_bm_of_probe()
152 bi = bm->bi; in ab8500_bm_of_probe()
155 if (bi->charge_full_design_uah < 0) in ab8500_bm_of_probe()
157 bi->charge_full_design_uah = 612000; in ab8500_bm_of_probe()
163 if ((bi->voltage_min_design_uv < 0) || in ab8500_bm_of_probe()
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/openbmc/linux/Documentation/devicetree/bindings/leds/
H A Dcommon.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
21 have to be tightly coupled with the LED device binding. They are represented
25 led-sources:
30 $ref: /schemas/types.yaml#/definitions/uint32-array
35 from the header include/dt-bindings/leds/common.h. If there is no
42 the header include/dt-bindings/leds/common.h. If there is no matching
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/openbmc/linux/Documentation/power/regulator/
H A Dconsumer.rst144 --------------------------------
163 ------------------------------
165 Bespoke or tightly coupled drivers may want to directly control regulator
199 they need to do low-level hardware access to regulators, with no involvement
202 - clocksource with a voltage-controlled oscillator and control logic to change
204 - thermal management firmware that can issue an arbitrary I2C transaction to
212 Bus-specific details, like I2C addresses or transfer rates are handled by the
225 regulator_list_voltage) to a hardware-specific voltage selector that can be
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dimx-regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
300 u32 ocmdr0; /* On-Chip Memory Descriptor Register */
302 u32 ocmdr3; /* On-Chip Memory Descriptor Register */
304 u32 tcmdr[4]; /* Generic Tightly Coupled Memory Descriptor Register */
/openbmc/qemu/docs/devel/
H A Dtracing.rst19 $ qemu --trace "memory_region_ops_*" ...
25 ``./configure --enable-trace-backends=BACKENDS`` was not explicitly specified.
27 Multiple patterns can be specified by repeating the ``--trace`` option::
29 $ qemu --trace "kvm_*" --trace "virtio_*" ...
32 file to avoid long command-line options::
36 $ qemu --trace events=/tmp/events ...
41 Sub-directory setup
42 -------------------
45 "trace-events" file. All directories which contain "trace-events" files must be
47 file. During build, the "trace-events" file in each listed subdirectory will be
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/openbmc/openbmc/poky/scripts/lib/resulttool/
H A Dregression.py1 # resulttool - regression analysis
6 # SPDX-License-Identifier: GPL-2.0-only
19 "trigger-build-posttrigger": {
35 "arch-qemu-quick": {
43 "arch-qemu-full-x86-or-x86_64": {
48 "select_tags":["machine", "toolchain-system"],
51 "arch-qemu-full-others": {
56 "select_tags":["machine", "toolchain-user"],
65 "exclude_tags": ["machine", "toolchain-system", "toolchain-user"]
73 "exclude_tags": ["machine", "toolchain-system", "toolchain-user"]
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/openbmc/linux/crypto/
H A Dessiv.c1 // SPDX-License-Identifier: GPL-2.0
6 * dm-crypt and fscrypt, which converts the initial vector for the skcipher
8 * skcipher key as encryption key. Usually, the input IV is a 64-bit sector
9 * number in LE representation zero-padded to the size of the IV, but this
14 * fscrypt, and the most relevant one for dm-crypt. However, dm-crypt
20 * flavor produced by this template is tightly coupled to the way dm-crypt
26 * adiantum length-preserving encryption mode
73 crypto_skcipher_clear_flags(tctx->u.skcipher, CRYPTO_TFM_REQ_MASK); in essiv_skcipher_setkey()
74 crypto_skcipher_set_flags(tctx->u.skcipher, in essiv_skcipher_setkey()
77 err = crypto_skcipher_setkey(tctx->u.skcipher, key, keylen); in essiv_skcipher_setkey()
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/openbmc/linux/drivers/clk/imx/
H A Dclk-scu.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
18 #include "clk-scu.h"
42 * struct clk_scu - Description of one SCU clock
60 * struct clk_gpr_scu - Description of one SCU GPR clock
76 * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
101 * struct imx_sc_msg_get_clock_rate - clock get rate protocol
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