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/openbmc/u-boot/doc/
H A DREADME.mpc85xx-spin-table1 Spin table in cache
3 As specified by ePAPR v1.1, the spin table needs to be in cached memory. After
4 DDR is initialized and U-Boot relocates itself into DDR, the spin table is
6 __secondary_start_page. For other cores to use the spin table, the booting
9 Core 0 sets up the reset page on the top 4K of memory (or 4GB if total memory
15 core 0 puts the physical address of the spin table (which is in release.S and
19 When secondary cores boot up from 0xffff_f000 page, they only have one default
20 TLB. While booting, they set up another TLB in AS=1 space and jump into
21 the new space. The new TLB covers the physical address of the spin table page,
22 with WIMGE =0b00100. Now secondary cores can keep polling the spin table
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/openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/css/
H A Dfont-awesome.min.css4 * -------------------------------------------------------
6 * can be found at: http://fortawesome.github.com/Font-Awesome/
9 * -------------------------------------------------------
10 * - The Font Awesome font is licensed under the SIL Open Font License - http://scripts.sil.org/OFL
11 * - Font Awesome CSS, LESS, and SASS files are licensed under the MIT License -
12 * http://opensource.org/licenses/mit-license.html
13 …* - The Font Awesome pictograms are licensed under the CC BY 3.0 License - http://creativecommons…
14 * - Attribution is no longer required in Font Awesome 3.0, but much appreciated:
15 * "Font Awesome by Dave Gandy - http://fortawesome.github.com/Font-Awesome"
18 * -------------------------------------------------------
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/openbmc/linux/Documentation/hwmon/
H A Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
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H A Ddrivetemp.rst1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
10 ANS T13/1699-D
11 Information technology - AT Attachment 8 - ATA/ATAPI Command Set (ATA8-ACS)
14 Information technology - SCSI Primary Commands - 4 (SPC-4)
17 Information technology - SCSI / ATA Translation - 5 (SAT-5)
21 -----------
34 ----------
36 Reading the drive temperature may reset the spin down timer on some drives.
43 change its mode (meaning the drive will not spin up). It is unknown if other
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/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2008-2012 Freescale Semiconductor, Inc.
7 #include <asm-offsets.h>
17 /* To boot secondary cpus, we need a place for them to start up.
21 * this page. We then set up the core, and head to
101 /* Enable/invalidate the I-Cache */
119 /* Enable/invalidate the D-Cache */
137 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
148 * 0-17 Reserved (logic 0s)
149 * 18-19 CHIP_ID, 2'b00 - SoC 1
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/openbmc/linux/tools/testing/selftests/kvm/
H A Dset_memory_region_test.c1 // SPDX-License-Identifier: GPL-2.0
56 struct kvm_run *run = vcpu->run; in vcpu_worker()
61 * Loop until the guest is done. Re-enter the guest on all MMIO exits, in vcpu_worker()
68 if (run->exit_reason == KVM_EXIT_IO) { in vcpu_worker()
77 if (run->exit_reason != KVM_EXIT_MMIO) in vcpu_worker()
80 TEST_ASSERT(!run->mmio.is_write, "Unexpected exit mmio write"); in vcpu_worker()
81 TEST_ASSERT(run->mmio.len == 8, in vcpu_worker()
82 "Unexpected exit mmio size = %u", run->mmio.len); in vcpu_worker()
84 TEST_ASSERT(run->mmio.phys_addr == MEM_REGION_GPA, in vcpu_worker()
86 run->mmio.phys_addr); in vcpu_worker()
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/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_rps.c1 // SPDX-License-Identifier: MIT
26 #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */
37 return -1; in cmp_u64()
49 return -1; in cmp_u32()
68 #define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x) in create_spin_counter()
76 obj = i915_gem_object_create_internal(vm->i915, 64 << 10); in create_spin_counter()
80 end = obj->base.size / sizeof(u32) - 1; in create_spin_counter()
113 loop = cs - base; in create_spin_counter()
134 GEM_BUG_ON(cs - base > end); in create_spin_counter()
190 mutex_lock(&rps->lock); in rps_set_check()
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H A Dselftest_engine_pm.c1 // SPDX-License-Identifier: GPL-2.0
25 return *a - *b; in cmp_u64()
76 struct intel_engine_cs *engine = ce->engine; in __measure_timestamps()
77 u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5); in __measure_timestamps()
78 u32 offset = i915_ggtt_offset(engine->status_page.vma); in __measure_timestamps()
96 cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000); in __measure_timestamps()
97 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004); in __measure_timestamps()
102 cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016); in __measure_timestamps()
103 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012); in __measure_timestamps()
117 while (READ_ONCE(sema[1]) == 0) /* wait for the gpu to catch up */ in __measure_timestamps()
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H A Dselftest_execlists.c1 // SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
47 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
58 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
62 return -ETIME; in wait_for_submit()
78 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset()
84 if (READ_ONCE(rq->fence.error)) in wait_for_reset()
88 if (rq->fence.error != -EIO) { in wait_for_reset()
90 engine->name, in wait_for_reset()
91 rq->fence.context, in wait_for_reset()
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/openbmc/linux/drivers/of/unittest-data/
H A Doverlay.dtso1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 hvac_2: hvac-large-1 {
9 compatible = "ot,hvac-large";
10 heat-range = <40 75>;
11 cool-range = <65 80>;
17 #address-cells = <1>;
18 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <1>;
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/openbmc/phosphor-fan-presence/monitor/example/
H A Dconfig.json7 "that are allowed to deviate from any given target by 15% for up-to 30",
11 "by -909 to accomodate how its hardware reacts to any given target. It",
19 "a poweron to allow the fan to spin-up."
38 "offset": -909
59 "a poweron to allow the fan to spin-up."
94 "deviate from any given target by 15% for up-to 30 seconds before",
108 "a poweron to allow the fan to spin-up. "
132 "OPTIONAL - A section to create `trust groups` consisting of fan tach",
136 "one of them shows a non-zero feedback speed. At any time all fan",
139 "one of them reports a non-zero feedback speed."
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/openbmc/linux/arch/sparc/include/asm/
H A Dbackoff.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * completion of the compare-and-swap instruction. Heavily
14 * When an atomic operation fails and needs to be retried, we spin a
16 * operation we double the spin count, realizing an exponential
19 * When we spin, we try to use an operation that will cause the
24 * On all cpus prior to SPARC-T4 we do three dummy reads of the
28 * For SPARC-T4 and later we have a special "pause" instruction
31 * unless a disrupting trap happens first. SPARC-T4 specifically
39 * on earlier chips, we shift the backoff value up by 7 bits. (Three
/openbmc/linux/drivers/net/can/softing/
H A Dsofting_main.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2010
5 * - Kurt Van Dijck, EIA Electronics
15 #define TX_ECHO_SKB_MAX (((TXMAX+1)/2)-1)
19 * is online (ie. up 'n running, not sleeping, not busoff
27 return (can->state <= CAN_STATE_ERROR_PASSIVE); in canif_is_active()
33 if (card->pdat->generation >= 2) { in softing_set_reset_dpram()
34 spin_lock_bh(&card->spin); in softing_set_reset_dpram()
35 iowrite8(ioread8(&card->dpram[DPRAM_V2_RESET]) & ~1, in softing_set_reset_dpram()
36 &card->dpram[DPRAM_V2_RESET]); in softing_set_reset_dpram()
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/openbmc/linux/arch/x86/include/asm/
H A Dspinlock.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * Simple spin lock operations. There are two variants, one clears IRQ's
19 * These are fair FIFO ticket locks, which support up to 2^16 CPUs.
24 /* How long a lock should spin before we consider blocking */
30 * Read-write spinlocks, allowing multiple readers
35 * can "mix" irq-safe locks - any writer needs to get a
36 * irq-safe write-lock, but readers can get non-irqsafe
37 * read-locks.
39 * On x86, we implement read-write locks using the generic qrwlock with
/openbmc/linux/Documentation/locking/
H A Dspinlocks.rst5 Lesson 1: Spin locks
20 there is only one thread-of-control within the region(s) protected by that
21 lock. This works well even under UP also, so the code does _not_ need to
22 worry about UP vs SMP issues: the spinlocks work correctly under both.
26 Documentation/memory-barriers.txt
33 spinlock for most things - using more than one spinlock can make things a
35 sequences that you **know** need to be split up: avoid it at all cost if you
45 NOTE! The spin-lock is safe only when you **also** use the lock itself
50 ----
52 Lesson 2: reader-writer spinlocks.
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H A Drt-mutex-design.rst2 RT-mutex implementation design
12 Documentation/locking/rt-mutex.rst. Although this document does explain problems
22 ----------------------------
49 A ---+
52 C +----+
54 B +-------->
59 -------------------------
74 -----------
80 - The PI chain is an ordered series of locks and processes that cause
86 - In this document, to differentiate from locks that implement
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/openbmc/linux/kernel/locking/
H A Dspinlock.c1 // SPDX-License-Identifier: GPL-2.0
10 * SMP and the DEBUG_SPINLOCK cases. (UP-nondebug inlines them)
33 * If lockdep is enabled then we use the non-preemption spin-ops
35 * not re-enabled during lock-acquire (which the preempt-spin-ops do):
63 * This could be a long-held lock. We both prepare to spin for a long
76 arch_##op##_relax(&lock->raw_lock); \
92 arch_##op##_relax(&lock->raw_lock); \
109 /* irq-disabling. We use the generic preemption-aware */ \
118 * Build preemption-friendly versions of the following
119 * lock-spinning functions:
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/openbmc/linux/arch/arc/include/asm/
H A Datomic-spinlock.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Non hardware assisted Atomic-R-M-W
8 * Locking would change to irq-disabling only (UP) and spinlocks (SMP)
25 WRITE_ONCE(v->counter, i); in arch_atomic_set()
37 v->counter c_op i; \
48 * spin lock/unlock provides the needed smp_mb() before/after \
51 temp = v->counter; \
53 v->counter = temp; \
66 * spin lock/unlock provides the needed smp_mb() before/after \
69 orig = v->counter; \
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/openbmc/linux/arch/arm64/kernel/
H A Dsmp_spin_table.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Spin Table SMP initialisation
50 return -ENODEV; in smp_spin_table_cpu_init()
55 ret = of_property_read_u64(dn, "cpu-release-addr", in smp_spin_table_cpu_init()
58 pr_err("CPU %d: missing or invalid cpu-release-addr property\n", in smp_spin_table_cpu_init()
72 return -ENODEV; in smp_spin_table_cpu_prepare()
75 * The cpu-release-addr may or may not be inside the linear mapping. in smp_spin_table_cpu_prepare()
83 return -ENOMEM; in smp_spin_table_cpu_prepare()
87 * endianness of the kernel. Therefore, any boot-loaders that in smp_spin_table_cpu_prepare()
89 * boot-loader's endianness before jumping. This is mandated by in smp_spin_table_cpu_prepare()
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/openbmc/linux/tools/testing/selftests/rcutorture/bin/
H A Djitterstart.sh2 # SPDX-License-Identifier: GPL-2.0+
4 # Start up the specified number of jitter.sh scripts in the background.
6 # Usage: . jitterstart.sh n jittering-dir duration [ sleepmax [ spinmax ] ]
8 # n: Number of jitter.sh scripts to start up.
9 # jittering-dir: Directory in which to put "jittering" file.
12 # spinmax: Maximum microseconds to spin, defaults to one millisecond.
19 if test -z "$jitter_n"
25 if test -z "$jittering_dir"
/openbmc/phosphor-fan-presence/docs/monitor/
H A Dset_func_on_present.md12 re-detected for that fan FRU and its contained rotors.
15 will need to spin up before being set back to functional, and if it never spins
16 up, there won't be additional errors.
46 "offset": -909
/openbmc/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_context.c2 * SPDX-License-Identifier: MIT
42 int err = -ENODEV; in live_nop_switch()
52 if (!DRIVER_CAPS(i915)->has_logical_contexts) in live_nop_switch()
61 err = -ENOMEM; in live_nop_switch()
88 i915_request_await_dma_fence(this, &rq->fence); in live_nop_switch()
96 intel_gt_set_wedged(engine->gt); in live_nop_switch()
98 err = -EIO; in live_nop_switch()
106 nctx, engine->name, ktime_to_ns(times[1] - times[0])); in live_nop_switch()
108 err = igt_live_test_begin(&t, i915, __func__, engine->name); in live_nop_switch()
127 i915_request_await_dma_fence(this, &rq->fence); in live_nop_switch()
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/openbmc/linux/Documentation/admin-guide/laptops/
H A Dlaptop-mode.rst2 How to conserve battery power using laptop-mode
12 ------------
14 Laptop mode is used to minimize the time that the hard disk needs to be spun up,
31 ------------
41 located in /etc/default/laptop-mode on Debian-based systems, or in
42 /etc/sysconfig/laptop-mode on other systems.
52 -------
54 * The downside of laptop mode is that you have a chance of losing up to 10
64 * If you mount some of your ext3/reiserfs filesystems with the -n option, then
67 wrong options -- or it will fail because it cannot write to /etc/mtab.
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/openbmc/linux/tools/memory-model/Documentation/
H A Dlocking.txt4 Locking is well-known and the common use cases are straightforward: Any
9 However, developers who would like to also access lock-protected shared
14 --------------------------
51 -------------------------------
86 Double-Checked Locking
87 ----------------------
90 double-checked locking work correctly, This litmus test illustrates
93 /* See Documentation/litmus-tests/locking/DCL-broken.litmus. */
118 /* See Documentation/litmus-tests/locking/DCL-fixed.litmus. */
143 In short, if you access a lock-protected variable without holding the
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/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dqcom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
18 Each board must specify a top-level board compatible string with the following
21 compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
92 ap-al02-c2
93 ap-al02-c6
94 ap-al02-c7
95 ap-al02-c8
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