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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Drockchip-i2s.yaml133 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
/openbmc/u-boot/include/dt-bindings/clock/
H A Drk3228-cru.h26 #define SCLK_I2S0 80 macro
H A Drk3188-cru-common.h31 #define SCLK_I2S0 75 macro
H A Drv1108-cru.h25 #define SCLK_I2S0 75 macro
H A Drk3328-cru.h29 #define SCLK_I2S0 41 macro
H A Drk3288-cru.h34 #define SCLK_I2S0 82 macro
/openbmc/linux/include/dt-bindings/clock/
H A Drk3188-cru-common.h31 #define SCLK_I2S0 75 macro
H A Drk3228-cru.h27 #define SCLK_I2S0 80 macro
H A Drk3128-cru.h28 #define SCLK_I2S0 80 macro
H A Drv1108-cru.h25 #define SCLK_I2S0 75 macro
H A Drk3328-cru.h30 #define SCLK_I2S0 41 macro
H A Drk3288-cru.h37 #define SCLK_I2S0 82 macro
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3188.c547 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
672 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
H A Dclk-rk3128.c358 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
H A Dclk-rk3228.c424 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
H A Dclk-rv1108.c508 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
H A Dclk-rk3288.c370 GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
/openbmc/u-boot/arch/arm/dts/
H A Drk3288-veyron-mickey.dts190 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
H A Drk3188.dtsi83 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
H A Drk322x.dtsi148 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
H A Drk3288-veyron.dtsi532 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-firefly-reload.dts222 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
H A Drk3188-bqedison2qc.dts451 clocks = <&cru SCLK_I2S0>;
H A Drk3188.dtsi171 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
H A Drk3066a.dtsi161 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;

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