/openbmc/linux/drivers/hsi/clients/ |
H A D | hsi_char.c | 342 static int hsc_rx_set(struct hsi_client *cl, struct hsc_rx_config *rxc) in hsc_rx_set() argument 347 if ((rxc->mode != HSI_MODE_STREAM) && (rxc->mode != HSI_MODE_FRAME)) in hsc_rx_set() 349 if ((rxc->channels == 0) || (rxc->channels > HSC_DEVS)) in hsc_rx_set() 351 if (rxc->channels & (rxc->channels - 1)) in hsc_rx_set() 353 if ((rxc->flow != HSI_FLOW_SYNC) && (rxc->flow != HSI_FLOW_PIPE)) in hsc_rx_set() 356 cl->rx_cfg.mode = rxc->mode; in hsc_rx_set() 357 cl->rx_cfg.num_hw_channels = rxc->channels; in hsc_rx_set() 358 cl->rx_cfg.flow = rxc->flow; in hsc_rx_set() 364 if (rxc->mode == HSI_MODE_FRAME) in hsc_rx_set() 370 static inline void hsc_rx_get(struct hsi_client *cl, struct hsc_rx_config *rxc) in hsc_rx_get() argument [all …]
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/openbmc/linux/drivers/mfd/ |
H A D | dln2.c | 193 struct dln2_rx_context *rxc; in dln2_transfer_complete() local 200 rxc = &rxs->slots[rx_slot]; in dln2_transfer_complete() 203 if (rxc->in_use && !rxc->urb) { in dln2_transfer_complete() 204 rxc->urb = urb; in dln2_transfer_complete() 205 complete(&rxc->done); in dln2_transfer_complete() 365 struct dln2_rx_context *rxc = &rxs->slots[*slot]; in find_free_slot() local 368 rxc->in_use = true; in find_free_slot() 398 struct dln2_rx_context *rxc; in free_rx_slot() local 406 rxc = &rxs->slots[slot]; in free_rx_slot() 407 rxc->in_use = false; in free_rx_slot() [all …]
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/openbmc/qemu/hw/rx/ |
H A D | rx-gdbsim.c | 85 RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_GET_CLASS(machine); in rx_gdbsim_init() local 102 object_initialize_child(OBJECT(machine), "mcu", &s->mcu, rxc->mcu_name); in rx_gdbsim_init() 106 rxc->xtal_freq_hz, &error_abort); in rx_gdbsim_init() 173 RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_CLASS(oc); in rx62n7_class_init() local 176 rxc->mcu_name = TYPE_R5F562N7_MCU; in rx62n7_class_init() 177 rxc->xtal_freq_hz = 12 * 1000 * 1000; in rx62n7_class_init() 183 RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_CLASS(oc); in rx62n8_class_init() local 186 rxc->mcu_name = TYPE_R5F562N8_MCU; in rx62n8_class_init() 187 rxc->xtal_freq_hz = 12 * 1000 * 1000; in rx62n8_class_init()
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H A D | rx62n.c | 220 RX62NClass *rxc = RX62N_MCU_GET_CLASS(dev); in rx62n_realize() local 238 rxc->ram_size, &error_abort); in rx62n_realize() 241 rxc->data_flash_size, &error_abort); in rx62n_realize() 244 rxc->rom_flash_size, &error_abort); in rx62n_realize() 278 RX62NClass *rxc = RX62N_MCU_CLASS(oc); in r5f562n7_class_init() local 280 rxc->ram_size = 64 * KiB; in r5f562n7_class_init() 281 rxc->rom_flash_size = 384 * KiB; in r5f562n7_class_init() 282 rxc->data_flash_size = 32 * KiB; in r5f562n7_class_init() 287 RX62NClass *rxc = RX62N_MCU_CLASS(oc); in r5f562n8_class_init() local 289 rxc->ram_size = 96 * KiB; in r5f562n8_class_init() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | micrel-ksz90x1.txt | 48 - rxc-skew-ps : Skew control of RXC pad 66 rxc-skew-ps=<0> actually results in -900 picoseconds adjustment. 74 The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps. 137 - rxc-skew-ps : Skew control of RX clock pad 165 A negative value can be assigned as rxc-skew-psec = <(-100)>;. 171 - rxc-skew-psec : Skew control of RX clock pad 191 rxc-skew-ps = <1800>; 201 rxc-skew-ps = <1800>;
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H A D | mediatek,star-emac.yaml | 51 mediatek,rmii-rxc: 55 PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin. 57 mediatek,rxc-inverse: 60 If present, indicates that clock on RXC pad will be inversed.
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H A D | mediatek-dwmac.yaml | 96 mediatek,rmii-rxc: 100 PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin. 118 mediatek,rxc-inverse:
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H A D | engleder,tsnep.yaml | 94 rxc-skew-ps = <1080>; 114 rxc-skew-ps = <1080>;
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/openbmc/u-boot/doc/device-tree-bindings/net/ |
H A D | micrel-ksz90x1.txt | 19 - rxc-skew-ps : Skew control of RXC pad 44 The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps. 107 - rxc-skew-ps : Skew control of RX clock pad 127 rxc-skew-ps = <1800>; 137 rxc-skew-ps = <1800>;
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/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt76x0/ |
H A D | initvals_init.h | 112 { MT_BBP(RXC, 1), 0x00000012 }, 113 { MT_BBP(RXC, 2), 0x00000011 }, 114 { MT_BBP(RXC, 3), 0x00000005 }, 115 { MT_BBP(RXC, 4), 0x00000000 }, 116 { MT_BBP(RXC, 5), 0xF977C4EC }, 117 { MT_BBP(RXC, 7), 0x00000090 },
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/openbmc/linux/drivers/spi/ |
H A D | spi-oc-tiny.c | 49 unsigned int txc, rxc; member 120 hw->rxc = 0; in tiny_spi_txrx_bufs() 163 if (hw->rxc + 1 == hw->len) { in tiny_spi_irq() 166 hw->rxc++; in tiny_spi_irq() 171 hw->rxc++; in tiny_spi_irq()
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/openbmc/linux/arch/arm/boot/dts/microchip/ |
H A D | sama5d3xmb_gmac.dtsi | 24 rxc-skew-ps = <3000>; 38 rxc-skew-ps = <3000>;
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H A D | sama5d3xcm_cmp.dtsi | 59 rxc-skew-ps = <3000>; 73 rxc-skew-ps = <3000>;
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/ |
H A D | dwmac-mediatek.c | 225 * and the property "rmii_rxc" indicates which pin(TXC/RXC) in mt2712_set_delay() 232 * to RXC pin, the reference clock will be adjusted in mt2712_set_delay() 233 * by RXC delay macro circuit. in mt2712_set_delay() 382 * and the property "rmii_rxc" indicates which pin(TXC/RXC) in mt8195_set_delay() 389 * to RXC pin, the reference clock will be adjusted in mt8195_set_delay() 390 * by RXC delay macro circuit. in mt8195_set_delay() 492 mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse"); in mediatek_dwmac_config_dt() 493 plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc"); in mediatek_dwmac_config_dt()
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/openbmc/u-boot/arch/arm/dts/ |
H A D | sama5d3xcm.dtsi | 50 rxc-skew-ps = <3000>; 64 rxc-skew-ps = <3000>;
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H A D | sama5d3xcm_cmp.dtsi | 49 rxc-skew-ps = <3000>; 63 rxc-skew-ps = <3000>;
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/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | fsl,asrc.txt | 25 - dma-names : Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc". 76 dma-names = "rxa", "rxb", "rxc",
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/openbmc/u-boot/include/dt-bindings/pinctrl/ |
H A D | pads-imx8qxp.h | 91 #define SC_P_SAI0_TXD 82 /* ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO,… 96 #define SC_P_SAI1_RXC 87 /* ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22… 105 #define SC_P_SPI0_CS1 96 /* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD,… 114 #define SC_P_FLEXCAN0_RX 105 /* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0… 117 #define SC_P_FLEXCAN1_TX 108 /* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.… 119 … 110 /* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */ 145 #define SC_P_CSI_D00 136 /* CI_PI.D02, ADMA.SAI0.RXC */ 148 #define SC_P_CSI_D03 139 /* CI_PI.D05, ADMA.SAI2.RXC */ 151 #define SC_P_CSI_D06 142 /* CI_PI.D08, ADMA.SAI3.RXC */
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/openbmc/linux/arch/arm/boot/dts/gemini/ |
H A D | gemini-nas4220b.dts | 114 pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC";
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H A D | gemini-sq201.dts | 189 pins = "Y7 GMAC0 RXC"; 205 pins = "Y11 GMAC1 RXC";
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/openbmc/linux/arch/powerpc/sysdev/ |
H A D | tsi108_dev.c | 130 * "txc-rxc-delay-disable" property enables this in tsi108_eth_of_init() 135 if (of_property_read_bool(phy, "txc-rxc-delay-disable")) in tsi108_eth_of_init()
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx6dl-mba6.dtsi | 21 rxc-skew-ps = <1860>;
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H A D | imx6q-mba6.dtsi | 27 rxc-skew-ps = <1860>;
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/openbmc/linux/drivers/tty/serial/ |
H A D | men_z135_uart.c | 218 * Read RXC register from hardware and return current FIFO fill size. 224 u16 rxc; in get_rx_fifo_content() local 232 rxc = rxc_lo | (rxc_hi << 8); in get_rx_fifo_content() 234 return rxc; in get_rx_fifo_content() 396 /* It's save to write to IIR[7:6] RXC[9:8] */ in men_z135_intr()
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/openbmc/linux/drivers/net/ethernet/micrel/ |
H A D | ks8851_common.c | 380 struct ks8851_rxctrl *rxc = &ks->rxctrl; in ks8851_irq() local 383 ks8851_wrreg16(ks, KS_MAHTR0, rxc->mchash[0]); in ks8851_irq() 384 ks8851_wrreg16(ks, KS_MAHTR1, rxc->mchash[1]); in ks8851_irq() 385 ks8851_wrreg16(ks, KS_MAHTR2, rxc->mchash[2]); in ks8851_irq() 386 ks8851_wrreg16(ks, KS_MAHTR3, rxc->mchash[3]); in ks8851_irq() 388 ks8851_wrreg16(ks, KS_RXCR2, rxc->rxcr2); in ks8851_irq() 389 ks8851_wrreg16(ks, KS_RXCR1, rxc->rxcr1); in ks8851_irq()
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