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/openbmc/linux/arch/x86/include/asm/uv/
H A Duv_mmrs.h555 unsigned long lb_hcerr:1; /* RW */
561 unsigned long lb_hcerr:1; /* RW */
563 unsigned long rh_hcerr:1; /* RW */
564 unsigned long lh0_hcerr:1; /* RW */
565 unsigned long lh1_hcerr:1; /* RW */
566 unsigned long gr0_hcerr:1; /* RW */
567 unsigned long gr1_hcerr:1; /* RW */
568 unsigned long ni0_hcerr:1; /* RW */
569 unsigned long ni1_hcerr:1; /* RW */
570 unsigned long lb_aoerr0:1; /* RW */
[all …]
/openbmc/openbmc/poky/meta/lib/oeqa/files/
H A Dbuildhistory_filelist2.txt122 -rw-r--r-- root root 45 ./etc/bash_completion
124 -rw-r--r-- root root 447 ./etc/bindresvport.blacklist
125 -rw-r--r-- root root 521 ./etc/build
126 -rw-r--r-- root root 2370 ./etc/busybox.links.nosuid
127 -rw-r--r-- root root 91 ./etc/busybox.links.suid
129 -rw-r--r-- root root 5340 ./etc/ca-certificates.conf
132 -rw-r--r-- root root 838 ./etc/dbus-1/session.conf
133 -rw-r--r-- root root 833 ./etc/dbus-1/system.conf
136 -rw-r--r-- root root 36 ./etc/default/mountall
137 -rw-r--r-- root root 52 ./etc/default/postinst
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H A Dbuildhistory_filelist1.txt122 -rw-r--r-- root root 45 ./etc/bash_completion
124 -rw-r--r-- root root 447 ./etc/bindresvport.blacklist
125 -rw-r--r-- root root 506 ./etc/build
126 -rw-r--r-- root root 2370 ./etc/busybox.links.nosuid
127 -rw-r--r-- root root 91 ./etc/busybox.links.suid
129 -rw-r--r-- root root 5340 ./etc/ca-certificates.conf
132 -rw-r--r-- root root 838 ./etc/dbus-1/session.conf
133 -rw-r--r-- root root 833 ./etc/dbus-1/system.conf
136 -rw-r--r-- root root 36 ./etc/default/mountall
137 -rw-r--r-- root root 52 ./etc/default/postinst
[all …]
/openbmc/linux/drivers/net/wireless/zydas/zd1211rw/
H A Dzd_rf_rf2959.c32 static int bits(u32 rw, int from, int to)
34 rw &= ~(0xffffffffU << (to+1));
35 rw >>= from;
36 return rw;
39 static int bit(u32 rw, int bit)
41 return bits(rw, bit, bit);
44 static void dump_regwrite(u32 rw)
46 int reg = bits(rw, 18, 22);
47 int rw_flag = bits(rw, 23, 23);
48 PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
[all …]
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.h12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
25 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
[all …]
/openbmc/u-boot/drivers/video/meson/
H A Dmeson_dw_hdmi.h12 * Bit 7 RW Reserved. Default 1.
13 * Bit 6 RW Reserved. Default 1.
14 * Bit 5 RW Reserved. Default 1.
15 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
17 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
20 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
22 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
24 * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset;
30 * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
31 * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0.
[all …]
/openbmc/linux/include/linux/mfd/
H A Dkhadas-mcu.h36 #define KHADAS_MCU_BOOT_MODE_REG 0x20 /* RW */
37 #define KHADAS_MCU_BOOT_EN_WOL_REG 0x21 /* RW */
38 #define KHADAS_MCU_BOOT_EN_RTC_REG 0x22 /* RW */
39 #define KHADAS_MCU_BOOT_EN_EXP_REG 0x23 /* RW */
40 #define KHADAS_MCU_BOOT_EN_IR_REG 0x24 /* RW */
41 #define KHADAS_MCU_BOOT_EN_DCIN_REG 0x25 /* RW */
42 #define KHADAS_MCU_BOOT_EN_KEY_REG 0x26 /* RW */
43 #define KHADAS_MCU_KEY_MODE_REG 0x27 /* RW */
44 #define KHADAS_MCU_LED_MODE_ON_REG 0x28 /* RW */
45 #define KHADAS_MCU_LED_MODE_OFF_REG 0x29 /* RW */
[all …]
H A Dstmfx.h16 #define STMFX_REG_SYS_CTRL 0x40 /* RW */
18 #define STMFX_REG_IRQ_OUT_PIN 0x41 /* RW */
19 #define STMFX_REG_IRQ_SRC_EN 0x42 /* RW */
21 #define STMFX_REG_IRQ_ACK 0x44 /* RW */
29 #define STMFX_REG_IRQ_GPI_SRC1 0x48 /* RW */
30 #define STMFX_REG_IRQ_GPI_SRC2 0x49 /* RW */
31 #define STMFX_REG_IRQ_GPI_SRC3 0x4A /* RW */
32 #define STMFX_REG_IRQ_GPI_EVT1 0x4C /* RW */
33 #define STMFX_REG_IRQ_GPI_EVT2 0x4D /* RW */
34 #define STMFX_REG_IRQ_GPI_EVT3 0x4E /* RW */
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Dregs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_FLA 0x0001C /* Flash Access - RW */
13 #define E1000_MDIC 0x00020 /* MDI Control - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
15 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
16 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
17 #define E1000_FEXT 0x0002C /* Future Extended - RW */
[all …]
/openbmc/qemu/hw/net/
H A De1000_regs.h37 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
38 #define E1000_EIAC 0x000DC /* Ext. Interrupt Auto Clear - RW */
39 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
40 #define E1000_EITR 0x000E8 /* Extended Interrupt Throttling Rate - RW */
41 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
42 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
43 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
44 #define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
45 #define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
46 #define E1000_FCRTV 0x05F40 /* Flow Control Refresh Timer Value - RW */
[all …]
/openbmc/linux/fs/smb/client/
H A Ddfs.h44 struct dfs_ref_walk *rw; in ref_walk_alloc() local
46 rw = kmalloc(sizeof(*rw), GFP_KERNEL); in ref_walk_alloc()
47 if (!rw) in ref_walk_alloc()
49 return rw; in ref_walk_alloc()
52 static inline void ref_walk_init(struct dfs_ref_walk *rw) in ref_walk_init() argument
54 memset(rw, 0, sizeof(*rw)); in ref_walk_init()
55 ref_walk_cur(rw) = ref_walk_start(rw); in ref_walk_init()
66 static inline void ref_walk_free(struct dfs_ref_walk *rw) in ref_walk_free() argument
68 struct dfs_ref *ref = ref_walk_start(rw); in ref_walk_free()
70 for (; ref <= ref_walk_end(rw); ref++) in ref_walk_free()
[all …]
/openbmc/linux/drivers/gpu/drm/arm/
H A Dhdlcd_regs.h16 #define HDLCD_REG_INT_RAWSTAT 0x0010 /* rw */
18 #define HDLCD_REG_INT_MASK 0x0018 /* rw */
20 #define HDLCD_REG_FB_BASE 0x0100 /* rw */
21 #define HDLCD_REG_FB_LINE_LENGTH 0x0104 /* rw */
22 #define HDLCD_REG_FB_LINE_COUNT 0x0108 /* rw */
23 #define HDLCD_REG_FB_LINE_PITCH 0x010c /* rw */
24 #define HDLCD_REG_BUS_OPTIONS 0x0110 /* rw */
25 #define HDLCD_REG_V_SYNC 0x0200 /* rw */
26 #define HDLCD_REG_V_BACK_PORCH 0x0204 /* rw */
27 #define HDLCD_REG_V_DATA 0x0208 /* rw */
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igb/
H A De1000_regs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_MDIC 0x00020 /* MDI Control - RW */
13 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
15 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
16 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
17 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
[all …]
/openbmc/openbmc-test-automation/docs/
H A Dcode_update.md106 -rw-r--r-- jenkins-op/jenkins-op 306804 2021-05-15 22:00 image-u-boot
107 -rw-r--r-- jenkins-op/jenkins-op 3039300 2021-05-12 03:32 image-kernel
108 -rw-r--r-- jenkins-op/jenkins-op 19861504 2021-05-15 22:00 image-rofs
109 -rw-r--r-- jenkins-op/jenkins-op 850304 2021-05-15 22:00 image-rwfs
110 -rw-r--r-- jenkins-op/jenkins-op 176 2021-05-15 22:00 MANIFEST
111 -rw-r--r-- jenkins-op/jenkins-op 272 2021-05-15 22:00 publickey
112 -rw-r--r-- jenkins-op/jenkins-op 128 2021-05-15 22:00 image-u-boot.sig
113 -rw-r--r-- jenkins-op/jenkins-op 128 2021-05-15 22:00 image-kernel.sig
114 -rw-r--r-- jenkins-op/jenkins-op 128 2021-05-15 22:00 image-rofs.sig
115 -rw-r--r-- jenkins-op/jenkins-op 128 2021-05-15 22:00 image-rwfs.sig
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h12 * by size in bits. For example [RW 32]. The access types are:
15 * RW - Read/Write
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
38 /* [RW 5] Parity mask register #0 read/write */
44 /* [RW 19] Interrupt mask register #0 read/write */
48 /* [RW 4] Parity mask register #0 read/write */
54 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
62 /* [RW 10] The number of free blocks below which the full signal to class 0
66 /* [RW 11] The number of free blocks above which the full signal to class 0
70 /* [RW 11] The number of free blocks below which the full signal to class 1
[all …]
/openbmc/linux/arch/ia64/include/asm/uv/
H A Duv_mmrs.h42 unsigned long vector_ : 8; /* RW */
43 unsigned long dm : 3; /* RW */
44 unsigned long destmode : 1; /* RW */
49 unsigned long m : 1; /* RW */
51 unsigned long apic_id : 32; /* RW */
178 unsigned long lb_hcerr : 1; /* RW, W1C */
179 unsigned long gr0_hcerr : 1; /* RW, W1C */
180 unsigned long gr1_hcerr : 1; /* RW, W1C */
181 unsigned long lh_hcerr : 1; /* RW, W1C */
182 unsigned long rh_hcerr : 1; /* RW, W1C */
[all …]
/openbmc/linux/arch/arc/include/asm/
H A Dspinlock.h79 static inline void arch_read_lock(arch_rwlock_t *rw) in arch_read_lock() argument
87 * if (rw->counter > 0) { in arch_read_lock()
88 * rw->counter--; in arch_read_lock()
101 : [rwlock] "r" (&(rw->counter)), in arch_read_lock()
109 static inline int arch_read_trylock(arch_rwlock_t *rw) in arch_read_trylock() argument
125 : [rwlock] "r" (&(rw->counter)), in arch_read_trylock()
134 static inline void arch_write_lock(arch_rwlock_t *rw) in arch_write_lock() argument
144 * if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) { in arch_write_lock()
145 * rw->counter = 0; in arch_write_lock()
158 : [rwlock] "r" (&(rw->counter)), in arch_write_lock()
[all …]
/openbmc/linux/arch/parisc/include/asm/
H A Dspinlock.h79 static inline int arch_read_trylock(arch_rwlock_t *rw) in arch_read_trylock() argument
85 arch_spin_lock(&(rw->lock_mutex)); in arch_read_trylock()
91 if (rw->counter > 0) { in arch_read_trylock()
92 rw->counter--; in arch_read_trylock()
96 arch_spin_unlock(&(rw->lock_mutex)); in arch_read_trylock()
103 static inline int arch_write_trylock(arch_rwlock_t *rw) in arch_write_trylock() argument
109 arch_spin_lock(&(rw->lock_mutex)); in arch_write_trylock()
117 if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) { in arch_write_trylock()
118 rw->counter = 0; in arch_write_trylock()
121 arch_spin_unlock(&(rw->lock_mutex)); in arch_write_trylock()
[all …]
/openbmc/linux/drivers/scsi/aic7xxx/
H A Daic79xx.reg101 access_mode RW
116 access_mode RW
133 access_mode RW
263 access_mode RW
281 access_mode RW
292 access_mode RW
302 access_mode RW
340 access_mode RW
350 access_mode RW
362 access_mode RW
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igc/
H A Digc_regs.h8 #define IGC_CTRL 0x00000 /* Device Control - RW */
10 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
11 #define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define IGC_MDIC 0x00020 /* MDI Control - RW */
13 #define IGC_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
14 #define IGC_VET 0x00038 /* VLAN Ether Type - RW */
19 #define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
20 #define IGC_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
23 #define IGC_EERD 0x12014 /* EEprom mode read - RW */
24 #define IGC_EEWR 0x12018 /* EEprom mode write - RW */
[all …]
/openbmc/linux/Documentation/hwmon/
H A Damc6821.rst30 temp1_min rw "
31 temp1_max rw "
32 temp1_crit rw "
38 temp2_min rw "
39 temp2_max rw "
40 temp2_crit rw "
47 fan1_min rw "
48 fan1_max rw "
50 fan1_div rw Fan divisor can be either 2 or 4.
52 pwm1 rw pwm1
[all …]
/openbmc/linux/block/
H A Dblk-throttle.c147 static uint64_t tg_bps_limit(struct throtl_grp *tg, int rw) in tg_bps_limit() argument
157 ret = tg->bps[rw][td->limit_index]; in tg_bps_limit()
161 tg->iops[rw][td->limit_index]) in tg_bps_limit()
167 if (td->limit_index == LIMIT_MAX && tg->bps[rw][LIMIT_LOW] && in tg_bps_limit()
168 tg->bps[rw][LIMIT_LOW] != tg->bps[rw][LIMIT_MAX]) { in tg_bps_limit()
171 adjusted = throtl_adjusted_limit(tg->bps[rw][LIMIT_LOW], td); in tg_bps_limit()
172 ret = min(tg->bps[rw][LIMIT_MAX], adjusted); in tg_bps_limit()
177 static unsigned int tg_iops_limit(struct throtl_grp *tg, int rw) in tg_iops_limit() argument
187 ret = tg->iops[rw][td->limit_index]; in tg_iops_limit()
191 tg->bps[rw][td->limit_index]) in tg_iops_limit()
[all …]
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-class-hwmon25 RW
36 RW
44 RW
56 RW
64 RW
150 RW
166 RW (but changing it should no more be necessary)
197 RW
206 RW
222 RW
[all …]
/openbmc/linux/drivers/char/mwave/
H A D3780i.h68 unsigned char ClockControl:1; /* RW: Clock control: 0=normal, 1=stop 3780i clocks */
69 unsigned char SoftReset:1; /* RW: Soft reset 0=normal, 1=soft reset active */
70 unsigned char ConfigMode:1; /* RW: Configuration mode, 0=normal, 1=config mode */
76 unsigned short EnableDspInt:1; /* RW: Enable DSP to X86 ISA interrupt 0=mask it, 1=enable it */
77 unsigned short MemAutoInc:1; /* RW: Memory address auto increment, 0=disable, 1=enable */
78 unsigned short IoAutoInc:1; /* RW: I/O address auto increment, 0=disable, 1=enable */
79 unsigned short DiagnosticMode:1; /* RW: Disgnostic mode 0=nromal, 1=diagnostic mode */
96 unsigned char IrqActiveLow:1; /* RW: IRQ active high or low: 0=high, 1=low */
97 unsigned char IrqPulse:1; /* RW: IRQ pulse or level: 0=level, 1=pulse */
98 unsigned char Irq:3; /* RW: IRQ selection */
[all …]
/openbmc/linux/arch/s390/include/asm/
H A Dspinlock.h99 #define arch_read_relax(rw) barrier() argument
100 #define arch_write_relax(rw) barrier() argument
105 static inline void arch_read_lock(arch_rwlock_t *rw) in arch_read_lock() argument
109 old = __atomic_add(1, &rw->cnts); in arch_read_lock()
111 arch_read_lock_wait(rw); in arch_read_lock()
114 static inline void arch_read_unlock(arch_rwlock_t *rw) in arch_read_unlock() argument
116 __atomic_add_const_barrier(-1, &rw->cnts); in arch_read_unlock()
119 static inline void arch_write_lock(arch_rwlock_t *rw) in arch_write_lock() argument
121 if (!__atomic_cmpxchg_bool(&rw->cnts, 0, 0x30000)) in arch_write_lock()
122 arch_write_lock_wait(rw); in arch_write_lock()
[all …]

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