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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun9i-a80-pll4-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml#
20 const: allwinner,sun9i-a80-pll4-clk
44 compatible = "allwinner,sun9i-a80-pll4-clk";
47 clock-output-names = "pll4";
H A Dqcom,gcc-ipq8064.yaml34 - description: PLL4 from LCC
41 - const: pll4
64 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
65 clock-names = "pxo", "cxo", "pll4";
H A Dallwinner,sun9i-a80-apb0-clk.yaml50 clocks = <&osc24M>, <&pll4>;
59 clocks = <&osc24M>, <&pll4>;
H A Dallwinner,sun9i-a80-gt-clk.yaml48 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
H A Dallwinner,sun4i-a10-ve-clk.yaml51 clocks = <&pll4>;
H A Dallwinner,sun9i-a80-ahb-clk.yaml48 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
H A Dallwinner,sun9i-a80-cpus-clk.yaml48 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
H A Dallwinner,sun4i-a10-mmc-clk.yaml82 clocks = <&osc24M>, <&pll4>;
H A Dqcom,gcc-apq8064.yaml48 - const: pll4
/openbmc/linux/drivers/clk/qcom/
H A Dlcc-ipq806x.c26 static struct clk_pll pll4 = { variable
35 .name = "pll4",
401 [PLL4] = &pll4.clkr,
450 /* Configure the rate of PLL4 if the bootloader hasn't already */ in lcc_ipq806x_probe()
453 clk_pll_configure_sr(&pll4, regmap, &pll4_config, true); in lcc_ipq806x_probe()
454 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_ipq806x_probe()
H A Dlcc-msm8960.c29 static struct clk_pll pll4 = { variable
38 .name = "pll4",
397 [PLL4] = &pll4.clkr,
470 /* Use the correct frequency plan depending on speed of PLL4 */ in lcc_msm8960_probe()
481 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_msm8960_probe()
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dti,j721e-cpb-audio.yaml19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
25 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
34 PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
H A Dti,j721e-cpb-ivi-audio.yaml24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
28 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
31 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
/openbmc/linux/drivers/clk/sunxi/
H A Dclk-sun9i-core.c18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
19 * PLL4 rate is calculated as follows
82 pr_err("Could not get registers for a80-pll4-clk: %pOFn\n", in sun9i_a80_pll4_setup()
90 CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
H A Dclk-sun9i-cpus.c62 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
86 /* calculate pre-divider if parent is pll4 */ in sun9i_a80_cpus_clk_round()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun50i_h6.h27 u32 pll4_cfg; /* 0x058 pll4 (ve) control */
47 u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */
48 u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */
71 u32 pll4_bias; /* 0x358 pll4 (ve) bias */
H A Dclock_sun8i_a83t.h23 u32 pll4_cfg; /* 0x18 pll4 ve control */
98 u32 pll4_bias_cfg; /* 0x22c PLL4 ve Bias config */
/openbmc/linux/include/dt-bindings/clock/
H A Dqcom,lcc-ipq806x.h9 #define PLL4 0 macro
H A Dqcom,lcc-msm8960.h9 #define PLL4 0 macro
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx8ulp.c37 static const char * const hifi_sels[] = { "frosc", "pll4", "pll4_pfd0", "sosc",
40 "pll4", "pll4", "pll4", "pll4", };
251 clks[IMX8ULP_CLK_PLL4] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "pll4", "pll4_pre_sel", base + 0x600); in imx8ulp_clk_cgc2_init()
252 clks[IMX8ULP_CLK_PLL4_VCODIV] = imx_clk_hw_divider("pll4_vcodiv", "pll4", base + 0x604, 0, 6); in imx8ulp_clk_cgc2_init()
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32mp1.txt25 MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
52 PLL children node for PLL1 to PLL4 : (see ref manual for details)
/openbmc/linux/drivers/clk/renesas/
H A Dr8a779g0-cpg-mssr.c73 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
247 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
259 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
H A Dr8a779f0-cpg-mssr.c179 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
191 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
/openbmc/u-boot/board/menlo/m53menlo/
H A Dm53menlo.c200 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to in enable_lvds_clock()
222 * Set LVDS clock to 9 MHz for the display. The PLL4 is set to in enable_lvds_etm0430g0dh6()
231 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to in enable_lvds_etm0700g0dh6()
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-odyssey.dts41 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */

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