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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,adsp.yaml19 - qcom,msm8226-adsp-pil
20 - qcom,msm8953-adsp-pil
21 - qcom,msm8974-adsp-pil
22 - qcom,msm8996-adsp-pil
23 - qcom,msm8996-slpi-pil
65 - qcom,msm8226-adsp-pil
66 - qcom,msm8953-adsp-pil
67 - qcom,msm8974-adsp-pil
68 - qcom,msm8996-adsp-pil
87 - qcom,msm8996-slpi-pil
[all …]
H A Dqcom,wcnss-pil.yaml4 $id: http://devicetree.org/schemas/remoteproc/qcom,wcnss-pil.yaml#
23 - qcom,pronto-v1-pil
24 - qcom,pronto-v2-pil
25 - qcom,pronto-v3-pil
27 - const: qcom,riva-pil
104 The iris subnode of the WCNSS PIL is used to describe the attached RF module
176 const: qcom,riva-pil
187 - qcom,pronto-v1-pil
188 - qcom,pronto-v2-pil
193 description: Deprecated for qcom,pronto-v1/2-pil
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H A Dqcom,msm8916-mss-pil.yaml4 $id: http://devicetree.org/schemas/remoteproc/qcom,msm8916-mss-pil.yaml#
20 - qcom,msm8909-mss-pil
21 - qcom,msm8916-mss-pil
22 - qcom,msm8953-mss-pil
23 - qcom,msm8974-mss-pil
25 - const: qcom,q6v5-pil
26 description: Deprecated, prefer using qcom,msm8916-mss-pil
74 (only valid for qcom,msm8953-mss-pil)
81 - const: mss # only valid for qcom,msm8953-mss-pil
88 description: MSS power domain supply (only valid for qcom,msm8974-mss-pil)
[all …]
H A Dqcom,msm8996-mss-pil.yaml4 $id: http://devicetree.org/schemas/remoteproc/qcom,msm8996-mss-pil.yaml#
20 - qcom,msm8996-mss-pil
21 - qcom,msm8998-mss-pil
22 - qcom,sdm660-mss-pil
23 - qcom,sdm845-mss-pil
70 - description: MSS power domain (only valid for qcom,sdm845-mss-pil)
77 - const: mss # only valid for qcom,sdm845-mss-pil
86 - description: PDC reset (only valid for qcom,sdm845-mss-pil)
92 - const: pdc_reset # only valid for qcom,sdm845-mss-pil
211 const: qcom,msm8996-mss-pil
[all …]
H A Dqcom,pil-info.yaml4 $id: http://devicetree.org/schemas/remoteproc/qcom,pil-info.yaml#
19 const: qcom,pil-reloc-info
41 pil-reloc@94c {
42 compatible = "qcom,pil-reloc-info";
H A Dqcom,q6v5.txt10 "qcom,ipq8074-wcss-pil"
11 "qcom,qcs404-wcss-pil"
43 qcom,ipq8074-wcss-pil:
45 qcom,qcs404-wcss-pil:
69 "qcom,qcs404-wcss-pil"
H A Dqcom,qcs404-cdsp-pil.yaml4 $id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-cdsp-pil.yaml#
19 - qcom,qcs404-cdsp-pil
121 compatible = "qcom,qcs404-cdsp-pil";
H A Dqcom,sdm845-adsp-pil.yaml4 $id: http://devicetree.org/schemas/remoteproc/qcom,sdm845-adsp-pil.yaml#
19 - qcom,sdm845-adsp-pil
124 compatible = "qcom,sdm845-adsp-pil";
/openbmc/linux/arch/sparc/include/asm/
H A Dirqflags_64.h14 #include <asm/pil.h>
23 "rdpr %%pil, %0" in arch_local_save_flags()
33 "wrpr %0, %%pil" in arch_local_irq_restore()
43 "wrpr %0, %%pil" in arch_local_irq_disable()
53 "wrpr 0, %%pil" in arch_local_irq_enable()
77 * The only values we ever program into the %pil are 0, in arch_local_irq_save()
80 * Since PIL_NMI is the largest %pil value and all bits are in arch_local_irq_save()
85 "rdpr %%pil, %0\n\t" in arch_local_irq_save()
87 "wrpr %1, 0x0, %%pil" in arch_local_irq_save()
H A Dpil.h9 * when SMP locking is an issue we reschedule the event into a PIL
14 * need to be done if the XCALL arrived while %pil==PIL_NORMAL_MAX.
/openbmc/qemu/hw/nvme/
H A Ddif.c69 int16_t pil = 0; in nvme_dif_pract_generate_dif_crc16() local
72 pil = ns->lbaf.ms - nvme_pi_tuple_size(ns); in nvme_dif_pract_generate_dif_crc16()
76 ns->lbasz + pil, apptag, in nvme_dif_pract_generate_dif_crc16()
80 NvmeDifTuple *dif = (NvmeDifTuple *)(mbuf + pil); in nvme_dif_pract_generate_dif_crc16()
83 if (pil) { in nvme_dif_pract_generate_dif_crc16()
84 crc = crc16_t10dif(crc, mbuf, pil); in nvme_dif_pract_generate_dif_crc16()
103 int16_t pil = 0; in nvme_dif_pract_generate_dif_crc64() local
106 pil = ns->lbaf.ms - 16; in nvme_dif_pract_generate_dif_crc64()
110 ns->lbasz + pil, apptag, in nvme_dif_pract_generate_dif_crc64()
114 NvmeDifTuple *dif = (NvmeDifTuple *)(mbuf + pil); in nvme_dif_pract_generate_dif_crc64()
[all …]
/openbmc/linux/arch/sparc/kernel/
H A Dirq_32.c106 * We keep a map of per-PIL enable interrupts. These get wired
123 unsigned int irq_alloc(unsigned int real_irq, unsigned int pil) in irq_alloc() argument
130 if (irq_table[i].real_irq == real_irq && irq_table[i].pil == pil) in irq_alloc()
142 irq_table[i].pil = pil; in irq_alloc()
153 /* Based on a single pil handler_irq may need to call several
161 unsigned int pil; in irq_link() local
168 pil = p->pil; in irq_link()
169 BUG_ON(pil >= SUN4D_MAX_IRQ); in irq_link()
170 p->next = irq_map[pil]; in irq_link()
171 irq_map[pil] = p; in irq_link()
[all …]
H A Dsun4d_irq.c90 * derived from the PIL we got interrupted on.
125 unsigned int pil; in sun4d_sbus_handler_irq() local
132 pil = sun4d_encode_irq(sbino, sbusl, idx); in sun4d_sbus_handler_irq()
134 p = irq_map[pil]; in sun4d_sbus_handler_irq()
147 void sun4d_handler_irq(unsigned int pil, struct pt_regs *regs) in sun4d_handler_irq() argument
151 int sbusl = pil_to_sbus[pil]; in sun4d_handler_irq()
156 cc_set_iclr(1 << pil); in sun4d_handler_irq()
163 if (pil == SUN4D_IPI_IRQ) in sun4d_handler_irq()
173 p = irq_map[pil]; in sun4d_handler_irq()
290 unsigned int pil, in _sun4d_build_device_irq() argument
[all …]
H A Dsun4v_ivec.S9 #include <asm/pil.h>
131 /* Signal the interrupt by setting (1 << pil) in %softint. */
204 rdpr %pil, %g2
205 wrpr %g0, PIL_NORMAL_MAX, %pil
234 rdpr %pil, %g2
235 wrpr %g0, PIL_NORMAL_MAX, %pil
315 rdpr %pil, %g2
316 wrpr %g0, PIL_NORMAL_MAX, %pil
345 rdpr %pil, %g2
346 wrpr %g0, PIL_NORMAL_MAX, %pil
H A Dirq.h10 unsigned int pil; member
79 unsigned int irq_alloc(unsigned int real_irq, unsigned int pil);
82 void handler_irq(unsigned int pil, struct pt_regs *regs);
93 void sun4d_handler_irq(unsigned int pil, struct pt_regs *regs);
H A Dcherrs.S105 rdpr %pil, %g2
106 wrpr %g0, PIL_NORMAL_MAX, %pil
147 rdpr %pil, %g2
148 wrpr %g0, PIL_NORMAL_MAX, %pil
491 rdpr %pil, %g2
492 wrpr %g0, PIL_NORMAL_MAX, %pil
527 rdpr %pil, %g2
528 wrpr %g0, PIL_NORMAL_MAX, %pil
563 rdpr %pil, %g2
564 wrpr %g0, PIL_NORMAL_MAX, %pil
H A Dtrampoline_32.S25 * in and sets PIL in %psr to 15, no irqs.
45 /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
99 /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
158 /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
H A Drtrap_64.S92 /* When returning from a NMI (%pil==15) interrupt we want to
103 /* Do not actually set the %pil here. We will do that
126 /* Do not actually set the %pil here. We will do that
147 * %pil.
160 wrpr 0, %pil
225 wrpr %l4, 0x0, %pil
/openbmc/linux/drivers/input/touchscreen/
H A Dwm9713.c44 * Set pil = 2 to use 400uA
45 * pil = 1 to use 200uA and
46 * pil = 0 to disable pressure measurement.
51 static int pil; variable
52 module_param(pil, int, 0);
53 MODULE_PARM_DESC(pil, "Set current used for pressure measurement.");
172 if (pil) { in wm9713_phy_init()
176 pil = 0; in wm9713_phy_init()
181 if (pil == 2) { in wm9713_phy_init()
185 } else if (pil) in wm9713_phy_init()
[all …]
H A Dwm9712.c44 * Set pil = 2 to use 400uA
45 * pil = 1 to use 200uA and
46 * pil = 0 to disable pressure measurement.
51 static int pil; variable
52 module_param(pil, int, 0);
53 MODULE_PARM_DESC(pil, "Set current used for pressure measurement.");
169 if (pil) { in wm9712_phy_init()
172 pil = 0; in wm9712_phy_init()
177 if (pil == 2) { in wm9712_phy_init()
181 } else if (pil) in wm9712_phy_init()
[all …]
H A Dwm9705.c31 * Set pil = 2 to use 400uA
32 * pil = 1 to use 200uA and
33 * pil = 0 to disable pressure measurement.
38 static int pil; variable
39 module_param(pil, int, 0);
40 MODULE_PARM_DESC(pil, "Set current used for pressure measurement.");
145 if (pil == 2) { in wm9705_phy_init()
149 } else if (pil) in wm9705_phy_init()
152 if (!pil) in wm9705_phy_init()
280 if (pil) { in wm9705_poll_touch()
[all …]
/openbmc/linux/drivers/remoteproc/
H A Dqcom_pil_info.c12 * The PIL relocation information region is used to communicate memory regions
41 np = of_find_compatible_node(NULL, NULL, "qcom,pil-reloc-info"); in qcom_pil_info_init()
52 pr_err("failed to map PIL relocation info region\n"); in qcom_pil_info_init()
65 * qcom_pil_info_store() - store PIL information of image in IMEM
102 pr_warn("insufficient PIL info slots\n"); in qcom_pil_info_store()
128 MODULE_DESCRIPTION("Qualcomm PIL relocation info");
/openbmc/linux/Documentation/devicetree/bindings/sram/
H A Dqcom,imem.yaml51 "^pil-reloc@[0-9a-f]+$":
52 $ref: /schemas/remoteproc/qcom,pil-info.yaml#
75 pil-reloc@94c {
76 compatible = "qcom,pil-reloc-info";
/openbmc/qemu/hw/intc/
H A Dslavio_intctl.c292 uint32_t pil = intbit_to_level[irq]; in slavio_set_irq() local
295 trace_slavio_set_irq(s->target_cpu, irq, pil, level); in slavio_set_irq()
296 if (pil > 0) { in slavio_set_irq()
299 s->irq_count[pil]++; in slavio_set_irq()
302 if (pil == 15) { in slavio_set_irq()
304 s->slaves[i].intreg_pending |= 1 << pil; in slavio_set_irq()
309 if (pil == 15) { in slavio_set_irq()
311 s->slaves[i].intreg_pending &= ~(1 << pil); in slavio_set_irq()
/openbmc/qemu/target/sparc/
H A Dint64_helper.c68 uint32_t pil = env->pil_in | in cpu_check_irqs() local
84 pil |= 1 << 14; in cpu_check_irqs()
91 if (pil < (2 << env->psrpil)) { in cpu_check_irqs()
105 if (pil & (1 << i)) { in cpu_check_irqs()
124 trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint, in cpu_check_irqs()

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