| /openbmc/linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | uncore-io.json | 12 …PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could…
27 …PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could…
41 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
51 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
61 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
71 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
81 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
91 "BriefDescription": "PCIe Completion Buffer Inserts; Port 0",
101 "BriefDescription": "PCIe Completion Buffer Inserts; Port 1",
111 "BriefDescription": "PCIe Completion Buffer Inserts; Port 2",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | uncore-io.json | 12 …PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could…
27 …PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could…
41 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
51 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
61 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
71 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
81 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
91 "BriefDescription": "PCIe Completion Buffer Inserts; Port 0",
101 "BriefDescription": "PCIe Completion Buffer Inserts; Port 1",
111 "BriefDescription": "PCIe Completion Buffer Inserts; Port 2",
[all …]
|
| /openbmc/linux/drivers/bcma/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
16 # Support for Block-I/O. SELECT this from the driver that needs it.
26 bool "Support for BCMA on PCI-host bus"
46 BCMA bus may have many versions of PCIe core. This driver
48 1) PCIe core working in clientmode
49 2) PCIe Gen 2 clientmode core
51 In general PCIe (Gen 2) clientmode core is required on PCIe
54 This driver is also prerequisite for a hostmode PCIe core
67 Driver for the Broadcom MIPS core attached to Broadcom specific
78 bool "ChipCommon-attached serial flash support"
[all …]
|
| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/ |
| H A D | PCIeFunction.v1_6_0.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
75 "NonEssentialInstrumentation": "A non-essential instrumentation.",
90 "PCIe",
94 "CXL": "A PCIe function supporting CXL extensions.",
95 "PCIe": "A standard PCIe function." string
105 "Physical": "A physical PCIe function.",
[all …]
|
| H A D | StorageController.v1_9_0.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
16 …ts this state for an ANA group provide non-optimized access characteristics, such as lower perform…
27 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
68 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
96 "description": "The available OEM-specific actions for this resource.",
97 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
107 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
122 … "description": "An array of links to volumes that are attached to this controller instance.",
126 … shall contain an array of links to resources of type `Volume` that are attached to this instance …
[all …]
|
| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/ |
| H A D | PCIeFunction.v1_6_0.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
75 "NonEssentialInstrumentation": "A non-essential instrumentation.",
90 "PCIe",
94 "CXL": "A PCIe function supporting CXL extensions.",
95 "PCIe": "A standard PCIe function." string
105 "Physical": "A physical PCIe function.",
[all …]
|
| H A D | StorageController.v1_9_0.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
16 …ts this state for an ANA group provide non-optimized access characteristics, such as lower perform…
27 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
68 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
96 "description": "The available OEM-specific actions for this resource.",
97 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
107 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
122 … "description": "An array of links to volumes that are attached to this controller instance.",
126 … shall contain an array of links to resources of type `Volume` that are attached to this instance …
[all …]
|
| /openbmc/linux/Documentation/PCI/ |
| H A D | pcieaer-howto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 :Authors: - T. Long Nguyen <tom.l.nguyen@intel.com>
9 - Yanmin Zhang <yanmin.zhang@intel.com>
17 ----------------
19 This guide describes the basics of the PCI Express (PCIe) Advanced Error
22 the PCIe AER driver.
25 What is the PCIe AER Driver?
26 ----------------------------
28 PCIe error signaling can occur on the PCIe link itself
29 or on behalf of transactions initiated on the link. PCIe
[all …]
|
| /openbmc/qemu/docs/ |
| H A D | bypass-iommu.txt | 10 passthrough devices with no-iommu mode and devices go through vIOMMU in
14 determine whether the devices attached on the PCI host bridge will bypass
18 the attached devices will go through vIOMMU by default.
31 qemu -device pxb-pcie,bus_nr=0x10,addr=0x1,bypass_iommu=true
33 qemu -machine virt,iommu=smmuv3,default_bus_bypass_iommu=true
35 qemu -machine q35,default_bus_bypass_iommu=true
40 qemu-system-aarch64 \
41 -machine virt,kernel_irqchip=on,iommu=smmuv3,default_bus_bypass_iommu=true \
42 -device pxb-pcie,bus_nr=0x10,id=pci.10,bus=pcie.0,addr=0x3.0x1 \
43 -device pxb-pcie,bus_nr=0x20,id=pci.20,bus=pcie.0,addr=0x3.0x2,bypass_iommu=true \
[all …]
|
| H A D | pcie.txt | 6 The doc proposes best practices on how to use PCI Express (PCIe) / PCI
10 Note that the PCIe features are available only when using the 'q35'
12 Other machine types do not use PCIe at this time.
25 QEMU does not have a clear socket-device matching mechanism
37 2.1 Root Bus (pcie.0)
43 Note: Integrated Endpoints are not hot-pluggable.
51 (2) PCI Express Root Ports (pcie-root-port), for starting exclusively
54 (3) PCI Express to PCI Bridge (pcie-pci-bridge), for starting legacy PCI
57 (4) Extra Root Complexes (pxb-pcie), if multiple PCI Express Root Buses
60 pcie.0 bus
[all …]
|
| /openbmc/qemu/docs/system/devices/ |
| H A D | cxl.rst | 4 targets accelerators and memory devices attached to a CXL host.
15 attached to CXL or PCI End Points. Alternatively there may be CXL Switches
16 with CXL and PCI Endpoints attached below them. In many cases additional
20 CXL elements are built upon an equivalent PCIe devices.
24 * Most conventional PCIe interfaces
26 - Configuration space access
27 - BAR mapped memory accesses used for registers and mailboxes.
28 - MSI/MSI-X
29 - AER
30 - DOE mailboxes
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | baikal,bt1-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
18 performed by software. There four in- and four outbound iATU regions
19 which can be used to emit all required TLP types on the PCIe bus.
[all …]
|
| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe endpoint interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller endpoint
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
[all …]
|
| /openbmc/linux/drivers/pci/controller/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
7 tristate "Aardvark PCIe controller"
13 Add support for Aardvark 64bit PCIe Host Controller. This
18 tristate "Altera PCIe controller"
21 Say Y here if you want to enable PCIe controller support on Altera
25 tristate "Altera PCIe MSI feature"
29 Say Y here if you want PCIe MSI support for the Altera FPGA.
38 tristate "Apple PCIe controller"
44 Say Y here if you want to enable PCIe controller support on Apple
45 system-on-chips, like the Apple M1. This is required for the USB
[all …]
|
| /openbmc/qemu/qapi/ |
| H A D | common.json | 1 # -*- Mode: Python -*-
100 # An enumeration of PCIe link speeds in units of GT/s
122 # An enumeration of PCIe link width
166 # Indicates whether a netfilter is attached to a netdev's transmit
169 # @all: the filter is attached both to the receive and the transmit
172 # @rx: the filter is attached to the receive queue of the netdev,
175 # @tx: the filter is attached to the transmit queue of the netdev,
186 # Key combinations to toggle input-linux between host and guest.
188 # @ctrl-ctrl: left and right control key
190 # @alt-alt: left and right alt key
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-miphy365x.txt | 5 for SATA and PCIe.
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
21 - #phy-cells : Should be 1 (See second example)
23 - PHY_TYPE_SATA
24 - PHY_TYPE_PCI
25 - reg : Address and length of register sets for each device in
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/arm/bcm/ |
| H A D | brcm,hr2.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
13 flash and a PCIe attached integrated switching engine.
16 - Florian Fainelli <f.fainelli@gmail.com>
23 - enum:
24 - ubnt,unifi-switch8
25 - const: brcm,bcm53342
26 - const: brcm,hr2
|
| /openbmc/bmcweb/redfish-core/schema/dmtf/installed/ |
| H A D | PCIeFunction_v1.xml | 1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: PCIeFunction v1.6.0 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2024 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
[all …]
|
| /openbmc/bmcweb/redfish-core/schema/dmtf/csdl/ |
| H A D | PCIeFunction_v1.xml | 1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: PCIeFunction v1.6.0 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2024 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
[all …]
|
| /openbmc/linux/drivers/net/can/sja1000/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
10 tristate "EMS CPC-PCI, CPC-PCIe and CPC-104P Card"
13 This driver is for the one, two or four channel CPC-PCI,
14 CPC-PCIe and CPC-104P cards from EMS Dr. Thomas Wuensche
15 (http://www.ems-wuensche.de).
18 tristate "EMS CPC-CARD Card"
21 This driver is for the one or two channel CPC-CARD cards from
22 EMS Dr. Thomas Wuensche (http://www.ems-wuensche.de).
25 tristate "Fintek F81601 PCIE to 2 CAN Controller"
28 This driver adds support for Fintek F81601 PCIE to 2 CAN
[all …]
|
| /openbmc/qemu/docs/config/ |
| H A D | q35-virtio-serial.cfg | 1 # q35 - VirtIO guest (serial console)
6 # $ qemu-system-x86_64 \
7 # -nodefaults \
8 # -readconfig q35-virtio-serial.cfg \
9 # -display none -serial mon:stdio
18 # ---------------------------------------------------------
20 # Using -nodefaults is required to have full control over
43 # We use '-display none' to prevent QEMU from creating a
45 # this specific configuration, and '-serial mon:stdio' to
79 [device "pcie.1"]
[all …]
|
| H A D | q35-virtio-graphical.cfg | 1 # q35 - VirtIO guest (graphical console)
6 # $ qemu-system-x86_64 \
7 # -nodefaults \
8 # -readconfig q35-virtio-graphical.cfg
17 # ---------------------------------------------------------
19 # Using -nodefaults is required to have full control over
74 [device "pcie.1"]
75 driver = "pcie-root-port"
76 bus = "pcie.0"
82 [device "pcie.2"]
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/net/bluetooth/ |
| H A D | brcm,bcm4377-bluetooth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/bluetooth/brcm,bcm4377-bluetooth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM4377 family PCIe Bluetooth Chips
10 - Sven Peter <sven@svenpeter.dev>
13 This binding describes Broadcom BCM4377 family PCIe-attached bluetooth chips
14 usually found in Apple machines. The Wi-Fi part of the chip is described in
15 bindings/net/wireless/brcm,bcm4329-fmac.yaml.
18 - $ref: bluetooth-controller.yaml#
[all …]
|
| /openbmc/linux/Documentation/driver-api/ |
| H A D | men-chameleon-bus.rst | 31 ----------------------
38 -----------------------------------------
40 The current implementation is limited to PCI and PCIe based carrier devices
44 - Multi-resource MCB devices like the VME Controller or M-Module carrier.
45 - MCB devices that need another MCB device, like SRAM for a DMA Controller's
47 - A per-carrier IRQ domain for carrier devices that have one (or more) IRQs
48 per MCB device like PCIe based carriers with MSI or MSI-X support.
55 - The MEN Chameleon Bus itself,
56 - drivers for MCB Carrier Devices and
57 - the parser for the Chameleon table.
[all …]
|
| /openbmc/linux/Documentation/networking/ |
| H A D | representors.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 used to control internal switching on SmartNICs. For the closely-related port
9 representors on physical (multi-port) switches, see
13 ----------
15 Since the mid-2010s, network cards have started offering more complex
16 virtualisation capabilities than the legacy SR-IOV approach (with its simple
17 MAC/VLAN-based switching model) can support. This led to a desire to offload
18 software-defined networks (such as OpenVSwitch) to these NICs to specify the
23 virtual switches and IOV devices. Just as each physical port of a Linux-
41 -----------
[all …]
|