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/openbmc/linux/drivers/platform/x86/
H A Dpanasonic-laptop.c53 * add /proc/acpi/pcc/brightness interface for HAL access
162 #define ACPI_PCC_CLASS "pcc"
283 static int acpi_pcc_write_sset(struct pcc_acpi *pcc, int func, int val) in acpi_pcc_write_sset() argument
297 status = acpi_evaluate_object(pcc->handle, METHOD_HKEY_SSET, in acpi_pcc_write_sset()
318 static int acpi_pcc_retrieve_biosdata(struct pcc_acpi *pcc) in acpi_pcc_retrieve_biosdata() argument
325 status = acpi_evaluate_object(pcc->handle, METHOD_HKEY_SINF, NULL, in acpi_pcc_retrieve_biosdata()
339 if (pcc->num_sifr < hkey->package.count) { in acpi_pcc_retrieve_biosdata()
341 pcc->num_sifr, hkey->package.count); in acpi_pcc_retrieve_biosdata()
349 pcc->sinf[i] = element->integer.value; in acpi_pcc_retrieve_biosdata()
353 pcc->sinf[hkey->package.count] = -1; in acpi_pcc_retrieve_biosdata()
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/openbmc/qemu/target/ppc/
H A Dcpu_init.c2161 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); variable
2164 pcc->init_proc = init_proc_405;
2165 pcc->check_pow = check_pow_nocheck;
2166 pcc->check_attn = check_attn_none;
2167 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2174 pcc->msr_mask = (1ull << MSR_WE) |
2184 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2185 pcc->excp_model = POWERPC_EXCP_40x;
2186 pcc->bus_model = PPC_FLAGS_INPUT_405;
2187 pcc->bfd_mach = bfd_mach_ppc_403;
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H A Dcompat.c124 static bool pcc_compat(PowerPCCPUClass *pcc, uint32_t compat_pvr, in pcc_compat() argument
142 if (compat->pvr > pcc->spapr_logical_pvr) { in pcc_compat()
146 if (!(pcc->pcr_supported & compat->pcr_level)) { in pcc_compat()
156 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); in ppc_check_compat() local
162 return pcc_compat(pcc, compat_pvr, min_compat_pvr, max_compat_pvr); in ppc_check_compat()
168 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(object_class_by_name(cputype)); in ppc_type_check_compat() local
169 return pcc_compat(pcc, compat_pvr, min_compat_pvr, max_compat_pvr); in ppc_type_check_compat()
176 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); in ppc_set_compat() local
204 env->spr[SPR_PCR] = pcr & pcc->pcr_mask; in ppc_set_compat()
H A Dgdbstub.c301 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); in gdb_gen_spr_feature() local
327 if (pcc->gdb_spr.xml) { in gdb_gen_spr_feature()
331 gdb_feature_builder_init(&builder, &pcc->gdb_spr, in gdb_gen_spr_feature()
625 void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc) in ppc_gdb_init() argument
627 if (pcc->insns_flags & PPC_FLOAT) { in ppc_gdb_init()
631 if (pcc->insns_flags & PPC_ALTIVEC) { in ppc_gdb_init()
636 if (pcc->insns_flags & PPC_SPE) { in ppc_gdb_init()
640 if (pcc->insns_flags2 & PPC2_VSX) { in ppc_gdb_init()
647 &pcc->gdb_spr, 0); in ppc_gdb_init()
/openbmc/linux/drivers/mailbox/
H A Dpcc.c6 * PCC (Platform Communication Channel) is defined in the ACPI 5.0+
11 * shared memory regions as defined in the PCC table entries. The PCC
12 * specification supports a Doorbell mechanism for the PCC clients
14 * is also specified in each PCC table entry.
18 * PCC Reads:
22 * * Client issues mbox_send_message() which rings the PCC doorbell
23 * for its PCC channel.
28 * PCC Writes:
33 * * Client issues mbox_send_message() which rings the PCC doorbell
34 * for its PCC channel.
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/openbmc/linux/Documentation/admin-guide/pm/
H A Dcpufreq_drivers.rst80 ``pcc-cpufreq``
86 * pcc-cpufreq.txt - PCC interface documentation
100 1.1 PCC interface
113 Processor Clocking Control (PCC) is an interface between the platform
117 The PCC driver (pcc-cpufreq) allows OSPM to take advantage of the PCC
120 OS utilizes the PCC interface to inform platform firmware what frequency the
126 1.1 PCC interface:
128 The complete PCC specification is available here:
131 PCC relies on a shared memory region that provides a channel for communication
132 between the OS and platform firmware. PCC also implements a "doorbell" that
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/openbmc/linux/drivers/acpi/
H A Dacpi_pcc.c6 * The PCC Address Space also referred as PCC Operation Region pertains to the
7 * region of PCC subspace that succeeds the PCC signature. The PCC Operation
8 * Region works in conjunction with the PCC Table(Platform Communications
9 * Channel Table). PCC subspaces that are marked for use as PCC Operation
10 * Regions must not be used as PCC subspaces for the standard ACPI features
12 * the PCC Table instead.
14 * This driver sets up the PCC Address Space and installs an handler to enable
15 * handling of PCC OpRegion in the firmware.
24 #include <acpi/pcc.h>
28 * to PCC commands
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H A Dcppc_acpi.c26 * called (PCC) Platform Communication Channel. This is a generic mailbox like
28 * See drivers/mailbox/pcc.c for details on PCC.
30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
55 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */
56 bool platform_owns_pcc; /* Ownership of PCC subspace */
57 unsigned int pcc_write_cnt; /* Running count of PCC write commands */
60 * Lock to provide controlled access to the PCC channel.
64 * before reading or writing to PCC subspace
83 /* Array to represent the PCC channel per subspace ID */
91 * include the type of register (e.g. PCC, System IO, FFH etc.)
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H A DKconfig273 select PCC
551 bool "ACPI PCC Address Space"
552 depends on PCC
555 The PCC Address Space also referred as PCC Operation Region pertains
556 to the region of PCC subspace that succeeds the PCC signature.
558 The PCC Operation Region works in conjunction with the PCC Table
559 (Platform Communications Channel Table). PCC subspaces that are
560 marked for use as PCC Operation Regions must not be used as PCC
562 MPST. These standard features must always use the PCC Table instead.
564 Enable this feature if you want to set up and install the PCC Address
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/openbmc/qemu/target/s390x/
H A Dcpu_features_def.h.inc315 /* Features exposed via the PCC instruction. */
316 DEF_FEAT(PCC_CMAC_DEA, "pcc-cmac-dea", PCC, 1, "PCC Compute-Last-Block-CMAC-Using-DEA")
317 DEF_FEAT(PCC_CMAC_TDEA_128, "pcc-cmac-tdea-128", PCC, 2, "PCC Compute-Last-Block-CMAC-Using-TDEA-12…
318 DEF_FEAT(PCC_CMAC_TDEA_192, "pcc-cmac-tdea-192", PCC, 3, "PCC Compute-Last-Block-CMAC-Using-TDEA-19…
319 DEF_FEAT(PCC_CMAC_ETDEA_128, "pcc-cmac-edea", PCC, 9, "PCC Compute-Last-Block-CMAC-Using-Encrypted-…
320 DEF_FEAT(PCC_CMAC_ETDEA_192, "pcc-cmac-etdea-128", PCC, 10, "PCC Compute-Last-Block-CMAC-Using-Encr…
321 DEF_FEAT(PCC_CMAC_TDEA, "pcc-cmac-etdea-192", PCC, 11, "PCC Compute-Last-Block-CMAC-Using-Encrypted…
322 DEF_FEAT(PCC_CMAC_AES_128, "pcc-cmac-aes-128", PCC, 18, "PCC Compute-Last-Block-CMAC-Using-AES-128")
323 DEF_FEAT(PCC_CMAC_AES_192, "pcc-cmac-aes-192", PCC, 19, "PCC Compute-Last-Block-CMAC-Using-AES-192")
324 DEF_FEAT(PCC_CMAC_AES_256, "pcc-cmac-aes-256", PCC, 20, "PCC Compute-Last-Block-CMAC-Using-AES-256")
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dpai_crypto.json727 "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING DEA",
728 "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-DEA function ending with CC=0"
734 "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING TDEA 128",
735 "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-TDEA-128 function ending with CC=0"
741 "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING TDEA 192",
742 "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-TDEA-192 function ending with CC=0"
748 "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED DEA",
749 "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-DEA function ending with CC=0"
755 "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED TDEA 128",
756 …"PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-TDEA- 128 function ending with C…
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/openbmc/phosphor-host-postd/
H A Dmain.cpp127 * Split input code into multiple 2 bytes PCC code, If the PCC code prefix
128 * matches the check code, store each PCC code in aspeedPCCBuffer, or clear
131 * Each PCC code contains one byte of port number (MSB) and another byte of
132 * partial postcode (LSB). To get a complete postcode, the PCC code should
134 * aspeedPCCBuffer contains enough PCC codes, the postcode will be assigned as
139 // Size of data coming from the PCC hardware in aspeedPCC()
141 // Required PCC count of a full postcode, if codeSize is 8 bytes, it means in aspeedPCC()
142 // it require 4 PCC codes in correct sequence to get a complete postcode. in aspeedPCC()
144 // A PCC buffer for storing PCC code in sequence. in aspeedPCC()
167 // keep the PCC code if codePtr[i] matches with 0x40XX as first PCC in aspeedPCC()
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/openbmc/qemu/hw/ppc/
H A Dpnv_core.c49 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); in pnv_core_cpu_reset() local
70 pcc->intc_reset(pc->chip, cpu); in pnv_core_cpu_reset()
307 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); in pnv_core_cpu_realize() local
313 pcc->intc_create(pc->chip, cpu, &local_err); in pnv_core_cpu_realize()
321 pcc->get_pir_tir(pc->chip, core_hwid, thread_index, &pir, &tir); in pnv_core_cpu_realize()
356 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc); in pnv_core_realize() local
397 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, in pnv_core_realize()
398 pc, name, pcc->xscom_size); in pnv_core_realize()
415 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); in pnv_core_cpu_unrealize() local
417 pcc->intc_destroy(pc->chip, cpu); in pnv_core_cpu_unrealize()
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H A Dpnv.c142 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); in pnv_dt_core() local
183 if (pcc->l1_dcache_size) { in pnv_dt_core()
185 pcc->l1_dcache_size))); in pnv_dt_core()
189 if (pcc->l1_icache_size) { in pnv_dt_core()
191 pcc->l1_icache_size))); in pnv_dt_core()
270 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); in pnv_dt_icp() local
279 pcc->get_pir_tir(chip, hwid, 0, &pir, NULL); in pnv_dt_icp()
1442 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); in pnv_chip_power8_instance_init() local
1459 chip8->num_phbs = pcc->num_phbs; in pnv_chip_power8_instance_init()
1481 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); in pnv_chip_icp_realize() local
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H A Dspapr_cpu_core.c33 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); in spapr_reset_vcpu() local
62 lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); in spapr_reset_vcpu()
90 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); in spapr_cpu_set_entry_state() local
100 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); in spapr_cpu_set_entry_state()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dimx7ulp-pcc-clock.yaml4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
7 title: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
28 The Peripheral Clock Control (PCC) is responsible for clock selection,
H A Dimx8ulp-pcc-clock.yaml4 $id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#
7 title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module
14 under the control of several CGCs & PCCs modules. The PCC modules control
/openbmc/linux/arch/mips/include/asm/dec/
H A Dkn01.h23 #define KN01_PCC (1*KN01_SLOT_SIZE) /* PCC (DC503) cursor */
50 #define KN01_CPU_INR_VIDEO 6 /* PCC area detect #2 */
63 #define KN01_CSR_CRSRTST (1<<12) /* PCC test output */
66 #define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */
/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dpcc.c11 #include <asm/arch/pcc.h>
120 printf("No PCS field for the PCC %d, clksrc type %d\n", in pcc_clock_sel()
133 printf("Not find the parent scg_clk in PCS of PCC %d, invalid scg_clk %d\n", clk, src); in pcc_clock_sel()
169 printf("No DIV/FRAC field for the PCC %d\n", clk); in pcc_clock_div_config()
221 printf("No PCS field for the PCC %d, clksrc type %d\n", in pcc_clock_get_clksrc()
234 printf("This pcc slot is not present = 0x%x\n", val); in pcc_clock_get_clksrc()
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dspp.h11 * struct dpu_hw_pcc_coeff - PCC coefficient structure for each color
25 * struct dpu_hw_pcc - pcc feature structure
43 * setup_pcc - setup dspp pcc
H A Ddpu_hw_dspp.c36 base = ctx->cap->sblk->pcc.base; in dpu_setup_dspp_pcc()
39 DRM_ERROR("invalid ctx %pK pcc base 0x%x\n", ctx, base); in dpu_setup_dspp_pcc()
44 DRM_DEBUG_DRIVER("disable pcc feature\n"); in dpu_setup_dspp_pcc()
/openbmc/linux/drivers/hwmon/
H A Dxgene-hwmon.c27 #include <acpi/pcc.h>
60 /* PCC defines */
68 * to PCC commands
156 /* Copy the message to the PCC comm space */ in xgene_hwmon_pcc_rd()
448 * If PCC, send a consumer command to Platform to get info in xgene_hwmon_evt_work()
527 * This function is called when the PCC Mailbox received a message
669 if (device_property_read_u32(&pdev->dev, "pcc-channel", in xgene_hwmon_probe()
671 dev_err(&pdev->dev, "no pcc-channel property\n"); in xgene_hwmon_probe()
689 dev_err(&pdev->dev, "PCC IRQ not supported\n"); in xgene_hwmon_probe()
710 dev_err(&pdev->dev, "Failed to get PCC comm region\n"); in xgene_hwmon_probe()
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/openbmc/linux/drivers/i2c/busses/
H A Di2c-xgene-slimpro.c12 #include <acpi/pcc.h>
187 /* Copy the message to the PCC comm space */ in slimpro_i2c_pcc_tx_prepare()
476 if (device_property_read_u32(&pdev->dev, "pcc-channel", in xgene_slimpro_i2c_probe()
484 dev_err(&pdev->dev, "PCC mailbox channel request failed\n"); in xgene_slimpro_i2c_probe()
492 dev_err(&pdev->dev, "PCC IRQ not supported\n"); in xgene_slimpro_i2c_probe()
514 dev_err(&pdev->dev, "Failed to get PCC comm region\n"); in xgene_slimpro_i2c_probe()
521 "Failed to ioremap PCC comm region\n"); in xgene_slimpro_i2c_probe()
/openbmc/linux/arch/sh/include/asm/
H A Dhd64461.h139 /* PCC Interface Status Register */
156 /* PCC General Control Register */
166 /* PCC Card Status Change Register */
176 /* PCC Card Status Change Interrupt Enable Register */
190 /* PCC Software Control Register */
/openbmc/linux/drivers/soc/hisilicon/
H A Dkunpeng_hccs.c30 #include <acpi/pcc.h>
34 /* PCC defines */
40 * to PCC commands
153 dev_err(dev, "PCC IRQ in PCCT is enabled.\n"); in hccs_register_pcc_channel()
162 dev_err(dev, "Failed to ioremap PCC communication region for channel-%d.\n", in hccs_register_pcc_channel()
186 * Poll PCC status register every 3us(delay_us) for maximum of in hccs_check_chan_cmd_complete()
187 * deadline_us(timeout_us) until PCC command complete bit is set(cond) in hccs_check_chan_cmd_complete()
194 dev_err(hdev->dev, "poll PCC status failed, ret = %d.\n", ret); in hccs_check_chan_cmd_complete()
219 /* Copy the message to the PCC comm space */ in hccs_pcc_cmd_send()
227 dev_err(hdev->dev, "Send PCC mbox message failed, ret = %d.\n", in hccs_pcc_cmd_send()
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