| /openbmc/linux/drivers/edac/ |
| H A D | octeon_edac-l2c.c | 21 #define EDAC_MOD_STR "octeon-l2c"
23 static void octeon_l2c_poll_oct1(struct edac_device_ctl_info *l2c) in octeon_l2c_poll_oct1() argument
31 edac_device_handle_ce(l2c, 0, 0, in octeon_l2c_poll_oct1()
36 edac_device_handle_ue(l2c, 0, 0, in octeon_l2c_poll_oct1()
46 edac_device_handle_ce(l2c, 0, 1, in octeon_l2c_poll_oct1()
51 edac_device_handle_ue(l2c, 0, 1, in octeon_l2c_poll_oct1()
60 static void _octeon_l2c_poll_oct2(struct edac_device_ctl_info *l2c, int tad) in _octeon_l2c_poll_oct2() argument
79 edac_device_handle_ue(l2c, tad, 1, buf2); in _octeon_l2c_poll_oct2()
85 edac_device_handle_ce(l2c, tad, 1, buf2); in _octeon_l2c_poll_oct2()
91 edac_device_handle_ue(l2c, tad, 1, buf2); in _octeon_l2c_poll_oct2()
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| H A D | thunderx_edac.c | 1501 /*---------------------- L2C driver ---------------------------------*/
1845 struct thunderx_l2c *l2c = container_of(msix, struct thunderx_l2c, in thunderx_l2c_threaded_isr() local
1848 unsigned long tail = ring_pos(l2c->ring_tail, ARRAY_SIZE(l2c->err_ctx)); in thunderx_l2c_threaded_isr()
1849 struct l2c_err_ctx *ctx = &l2c->err_ctx[tail]; in thunderx_l2c_threaded_isr()
1865 switch (l2c->pdev->device) { in thunderx_l2c_threaded_isr()
1885 dev_err(&l2c->pdev->dev, "Unsupported device: %04x\n", in thunderx_l2c_threaded_isr()
1886 l2c->pdev->device); in thunderx_l2c_threaded_isr()
1890 while (CIRC_CNT(l2c->ring_head, l2c->ring_tail, in thunderx_l2c_threaded_isr()
1891 ARRAY_SIZE(l2c->err_ctx))) { in thunderx_l2c_threaded_isr()
1894 l2c->edac_dev->ctl_name, reg_int_name, ctx->reg_int, in thunderx_l2c_threaded_isr()
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| H A D | Makefile | 74 obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o
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| /openbmc/u-boot/arch/mips/lib/ |
| H A D | cache.c | 22 bool l2c = false; in probe_l2() local
30 l2c = conf2 & MIPS_CONF_M; in probe_l2()
31 if (l2c) in probe_l2()
32 l2c = read_c0_config3() & MIPS_CONF_M; in probe_l2()
33 if (l2c) in probe_l2()
34 l2c = read_c0_config4() & MIPS_CONF_M; in probe_l2()
35 if (l2c) in probe_l2()
36 l2c = read_c0_config5() & MIPS_CONF5_L2C; in probe_l2()
39 if (l2c && config_enabled(CONFIG_MIPS_CM)) { in probe_l2()
41 } else if (l2c) { in probe_l2()
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| H A D | cache_init.S | 125 * by Config2. The Config5.L2C bit indicates whether this is the case,
138 /* Check Config5.L2C is set */
143 /* Config5.L2C is set */
186 * For pre-r6 systems, or r6 systems with Config5.L2C==0, probe the L2
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| /openbmc/linux/arch/arm/mm/ |
| H A D | cache-l2x0.c | 160 * L2C-210 specific code.
162 * The L2C-2x0 PA, set/way and sync operations are atomic, but we must
171 * we use sync_reg_offset here so we can share some of this with L2C-310.
240 .type = "L2C-210",
259 * L2C-220 specific code.
390 * we write to them as part of the L2C enable sequence so they in l2c220_enable()
405 .type = "L2C-220",
424 * L2C-310 specific code.
426 * Very similar to L2C-210, the PA, set/way and sync operations are atomic,
460 * prevents merging writes after the sync operation, until another L2C
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| H A D | l2c-l2x0-resume.S | 3 * L2C-310 early resume code. This can be used by platforms to restore
21 @ r1 = phys address of L2C-310 controller
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| H A D | Makefile | 92 obj-$(CONFIG_OUTER_CACHE) += l2c-common.o
95 obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o l2c-l2x0-resume.o
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| /openbmc/linux/arch/arm/include/asm/hardware/ |
| H A D | cache-l2x0.h | 89 /* L2C auxiliary control register - bits common to L2C-210/220/310 */
96 /* L2C-210/220 common bits */
107 /* L2C-210 specific bits */
111 /* L2C-220 specific bits */
117 /* L2C-310 specific bits */
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| /openbmc/linux/arch/powerpc/platforms/4xx/ |
| H A D | soc.c | 32 /* Issue L2C diagnostic command */
50 printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n", in l2c_error_handler()
56 printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n", in l2c_error_handler()
65 printk(KERN_EMERG "L2C: LRU error\n"); in l2c_error_handler()
115 if (request_irq(irq, l2c_error_handler, 0, "L2C", 0) < 0) { in ppc4xx_l2c_probe()
116 printk(KERN_ERR "Cannot install L2C error handler" in ppc4xx_l2c_probe()
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| /openbmc/linux/arch/mips/include/asm/octeon/ |
| H A D | cvmx-l2c.h | 29 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
52 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
68 /* L2C Performance Counter events. */
127 /* L2C Performance Counter events for Octeon2. */
269 * of L2C debug features.
297 * Returns l2c tag structure for line requested.
324 * of L2C debug features.
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| H A D | cvmx-npi-defs.h | 2231 uint64_t l2c:1; member
2263 uint64_t l2c:1;
2299 uint64_t l2c:1; member
2333 uint64_t l2c:1;
2370 uint64_t l2c:1; member
2404 uint64_t l2c:1;
2437 uint64_t l2c:1; member
2471 uint64_t l2c:1;
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| /openbmc/linux/Documentation/devicetree/bindings/cache/ |
| H A D | andestech,ax45mp-cache.yaml | 14 A level-2 cache (L2C) is used to improve the system performance by providing
15 a large amount of cache line entries and reasonable access delays. The L2C
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| /openbmc/linux/arch/mips/cavium-octeon/executive/ |
| H A D | cvmx-l2c.c | 29 * Implementation of the Level 2 Cache (L2C) control,
36 #include <asm/octeon/cvmx-l2c.h>
93 /* A UMSK setting which blocks all L2C Ways is an error on some chips */ in cvmx_l2c_set_core_way_partition()
149 /* A UMSK setting which blocks all L2C Ways is an error on some chips */ in cvmx_l2c_set_hw_way_partition()
206 …cvmx_dprintf("L2C performance counter events are different for this chip, mapping 'event' to cvmx_… in cvmx_l2c_config_perf()
208 cvmx_dprintf("L2C counters don't support clear on read for this chip\n"); in cvmx_l2c_config_perf()
523 * Internal l2c tag types. These are converted to a generic structure
580 * Function to read a L2C tag. This code make the current core
635 "ld %[tag_val], 0(%[tag_addr])\n\t" /* Read L2C tag data */ in __read_l2_tag()
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| H A D | Makefile | 12 obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
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| /openbmc/libpldm/tests/dsp/ |
| H A D | pdr.cpp | 738 auto l2c = pldm_entity_association_tree_add( in TEST() local
740 EXPECT_NE(l2c, nullptr); in TEST()
763 EXPECT_EQ(pldm_entity_is_node_parent(l2c), false); in TEST()
773 pldm_entity parentL2c = pldm_entity_get_parent(l2c); in TEST()
776 EXPECT_EQ(pldm_entity_is_exist_parent(l2c), true); in TEST()
869 pldm_entity p2c = pldm_entity_extract(l2c); in TEST()
1145 auto l2c = pldm_entity_association_tree_add( in TEST() local
1147 EXPECT_NE(l2c, nullptr); in TEST()
1462 auto l2c = pldm_entity_association_tree_add( in TEST() local
1464 EXPECT_NE(l2c, nullptr); in TEST()
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| /openbmc/linux/arch/csky/kernel/ |
| H A D | cpu-probe.c | 42 seq_printf(m, "ccr2 (L2C) : 0x%08x\n", mfcr_ccr2()); in percpu_print()
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| /openbmc/u-boot/arch/arm/mach-mediatek/mt7629/ |
| H A D | init.c | 89 /* disable L2C shared mode */ in mach_cpu_init()
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| /openbmc/u-boot/arch/arm/mach-orion5x/ |
| H A D | cpu.c | 263 /* Disable L2C pre fetch - Set bit 24 */ in arch_misc_init()
265 /* enable L2C - Set bit 22 */ in arch_misc_init()
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| /openbmc/u-boot/arch/arm/mach-kirkwood/ |
| H A D | cpu.c | 288 /* Disable L2C pre fetch - Set bit 24 */ in arch_misc_init()
290 /* enable L2C - Set bit 22 */ in arch_misc_init()
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| /openbmc/linux/arch/arm/include/asm/ |
| H A D | outercache.h | 27 /* This is an ARM L2C thing */
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| /openbmc/linux/arch/arm/kernel/ |
| H A D | irq.c | 144 pr_err("L2C: failed to init: %d\n", ret); in init_IRQ()
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| /openbmc/linux/drivers/staging/octeon/ |
| H A D | octeon-stubs.h | 1022 uint64_t l2c:1; member
1056 uint64_t l2c:1; member
1091 uint64_t l2c:1; member
1122 uint64_t l2c:1; member
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| /openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z10/ |
| H A D | extended.json | 125 "BriefDescription": "L2C Stores Sent",
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| /openbmc/qemu/hw/misc/ |
| H A D | arm_l2x0.c | 29 /* L2C-310 r3p2 */
|