| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | rockchip-i2s.yaml | 133 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | rk3188-cru-common.h | 112 #define HCLK_I2S0 454 macro
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| H A D | rk3288-cru.h | 172 #define HCLK_I2S0 462 macro
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | rk3188-cru-common.h | 114 #define HCLK_I2S0 454 macro
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| H A D | px30-cru.h | 138 #define HCLK_I2S0 262 macro
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| H A D | rk3288-cru.h | 180 #define HCLK_I2S0 462 macro
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| H A D | rockchip,rv1126-cru.h | 269 #define HCLK_I2S0 205 macro
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| /openbmc/linux/drivers/clk/rockchip/ |
| H A D | clk-rk3188.c | 638 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
733 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
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| H A D | clk-rv1126.c | 633 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_pdaudio", 0,
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| H A D | clk-rk3288.c | 677 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
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| H A D | clk-px30.c | 840 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 2, GFLAGS),
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| H A D | clk-rk3399.c | 1022 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | rk3288-veyron-mickey.dts | 190 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
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| H A D | rk3188.dtsi | 83 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
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| H A D | rk3288-veyron.dtsi | 532 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
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| H A D | rk3288.dtsi | 656 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
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| /openbmc/linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3288-firefly-reload.dts | 222 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
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| H A D | rk3188.dtsi | 171 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
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| H A D | rk3066a.dtsi | 161 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
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| H A D | rk3288.dtsi | 965 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
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| /openbmc/linux/arch/arm64/boot/dts/rockchip/ |
| H A D | px30.dtsi | 393 clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
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