/openbmc/linux/include/kvm/ |
H A D | arm_vgic.h | 39 VGIC_V2, /* Good ol' GICv2 */ 67 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */ 145 u8 targets; /* GICv2 target VCPUs mask */ 148 u8 source; /* GICv2 SGIs only */ 149 u8 active_source; /* GICv2 SGIs only */ 229 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ 234 #define KVM_VGIC_IMP_REV_2 2 /* GICv2 restorable groups */ 238 /* Userspace can write to GICv2 IGROUPR */ 249 /* either a GICv2 CPU interface */
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/openbmc/linux/Documentation/virt/kvm/devices/ |
H A D | arm-vgic.rst | 17 guest GICv2 through this interface. For information on creating a guest GICv3 19 create both a GICv3 and GICv2 device on the same VM. 58 GICv2 specs. Getting or setting such a register has the same effect as 65 GICv2 is changed in a way directly observable by the guest or userspace. 92 defined in the GICv2 specs. Getting or setting such a register has the 96 fixed format for our implementation that fits with the model of a "GICv2 112 similar to GICv2's GICH_APR.
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/openbmc/linux/arch/arm64/boot/dts/arm/ |
H A D | foundation-v8-psci.dts | 4 * ARMv8 Foundation model DTS (GICv2+PSCI configuration) 8 #include "foundation-v8-gicv2.dtsi"
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H A D | foundation-v8.dts | 5 * ARMv8 Foundation model DTS (GICv2 configuration) 9 #include "foundation-v8-gicv2.dtsi"
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H A D | foundation-v8-gicv2.dtsi | 4 * ARMv8 Foundation model DTS (GICv2 configuration)
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/openbmc/linux/Documentation/devicetree/bindings/pci/ |
H A D | brcm,stb-pcie.yaml | 153 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 154 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 155 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 156 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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/openbmc/linux/arch/arm64/kvm/vgic/ |
H A D | vgic-mmio-v2.c | 20 * Revision 1: Report GICv2 interrupts as group 0 instead of group 1 370 /* GICv2 hardware systems support max. 32 groups */ in vgic_mmio_read_apr() 382 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_read_apr() 396 /* GICv2 hardware systems support max. 32 groups */ in vgic_mmio_write_apr() 408 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_write_apr()
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H A D | vgic-init.c | 33 * structures. Can be executed lazily for GICv2. 79 * which had no chance yet to check the availability of the GICv2 in kvm_vgic_create() 156 * initialization when using a virtual GICv2. in kvm_vgic_dist_init() 419 * is a GICv2. A GICv3 must be explicitly initialized by userspace using the 430 * for the legacy case of a GICv2. Any other type must in vgic_lazy_init()
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H A D | vgic-v2.c | 194 /* The GICv2 LR only holds five bits of priority. */ in vgic_v2_populate_lr() 343 kvm_err("GICv2 not supported in protected mode\n"); in vgic_v2_probe() 382 kvm_err("Cannot register GICv2 KVM device\n"); in vgic_v2_probe()
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H A D | vgic-v3.c | 272 * If we are emulating a GICv3, we do it in an non-GICv2-compatible in vgic_v3_enable() 672 kvm_err("Cannot register GICv2 KVM device.\n"); in vgic_v3_probe() 685 kvm_info("disabling GICv2 emulation\n"); in vgic_v3_probe() 725 * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen in vgic_v3_load()
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H A D | vgic-mmio.c | 361 * GICv2 SGIs are terribly broken. We can't restore in vgic_uaccess_write_spending() 453 * More fun with GICv2 SGIs! If we're clearing one of them in vgic_uaccess_write_cpending() 481 * For GICv2 private interrupts we don't have to do anything because 585 * The GICv2 architecture indicates that the source CPUID for in vgic_mmio_change_active() 593 * for a GICv2 VM on some GIC implementations. Oh well. in vgic_mmio_change_active()
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/openbmc/u-boot/arch/arm/lib/ |
H A D | gic_64.S | 68 * For Gicv2: 163 * For Gicv2: 184 * For Gicv2:
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/openbmc/linux/drivers/irqchip/ |
H A D | irq-gic.c | 900 .name = "GICv2", 1302 * first page of a GICv2. in gic_check_eoimode() 1308 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); in gic_check_eoimode() 1317 * The first page was that of a GICv2, and in gic_check_eoimode() 1319 * to be a GICv2, and update the mapping. in gic_check_eoimode() 1321 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", in gic_check_eoimode() 1329 * We detected *two* initial GICv2 pages in a in gic_check_eoimode() 1330 * row. Could be a GICv2 aliased over two 64kB in gic_check_eoimode() 1338 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", in gic_check_eoimode() 1346 * Verify that we have the first 4kB of a GICv2 in gic_check_eoimode() [all …]
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/openbmc/linux/include/linux/irqchip/ |
H A D | arm-vgic-info.h | 14 /* Full GICv2 */
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/openbmc/linux/tools/testing/selftests/kvm/aarch64/ |
H A D | vgic_init.c | 138 * ARM_VGIC (GICv2 or GICv3) device gets created with an overlapping 139 * DIST/REDIST (or DIST/CPUIF for GICv2). Assumption is 4 vcpus are going to be 141 * and a DIST region is set @0x70000. The GICv2 case sets a CPUIF @0x0 and a 148 struct vgic_region_attr rdist; /* CPU interface in GICv2*/ in subtest_dist_rdist() 762 print_skip("No GICv2 nor GICv3 support"); in main()
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | arm,gic.yaml | 101 For GICv2 with virtualization extensions, additional regions are 202 // GICv2
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/openbmc/linux/arch/arm/boot/dts/broadcom/ |
H A D | bcm2711.dtsi | 13 interrupt-parent = <&gicv2>; 56 gicv2: interrupt-controller@40041000 { label 566 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 568 <0 0 0 2 &gicv2 GIC_SPI 144 570 <0 0 0 3 &gicv2 GIC_SPI 145 572 <0 0 0 4 &gicv2 GIC_SPI 146
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/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/ |
H A D | 0006-feat-corstone1000-include-platform-header-file.patch | 21 #include <drivers/arm/gicv2.h>
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H A D | 0004-fix-corstone1000-clean-the-cache-and-disable-interru.patch | 25 +#include <drivers/arm/gicv2.h>
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/openbmc/qemu/docs/system/arm/ |
H A D | virt.rst | 37 with GICv2. ITS is selected by default with GICv3 (>= virt-2.7). Note 146 GICv2. Note that this limits the number of CPUs to 8.
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/openbmc/linux/Documentation/devicetree/bindings/gpio/ |
H A D | gpio-xgene-sb.txt | 12 | (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
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/openbmc/qemu/hw/intc/ |
H A D | gic_internal.h | 152 * GICv2 and GICv2 with security extensions:
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H A D | arm_gicv2m.c | 2 * GICv2m extension for MSI/MSI-x support with a GICv2-based system
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/openbmc/qemu/include/hw/intc/ |
H A D | arm_gic_common.h | 104 /* If we present the GICv2 without security extensions to a guest,
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/openbmc/linux/arch/arm64/kvm/hyp/ |
H A D | vgic-v3-sr.c | 264 * Group0 interrupt (as generated in GICv2 mode) to be in __vgic_v3_activate_traps() 412 * - [63] MMIO (GICv2) capable 420 * To check whether we have a MMIO-based (GICv2 compatible) in __vgic_v3_get_gic_config()
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