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Searched full:emc_cfg (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/memory/tegra/
H A Dtegra30-emc.c44 #define EMC_CFG 0x00c macro
370 u32 emc_cfg; member
554 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG); in emc_prepare_timing_change()
577 if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) { in emc_prepare_timing_change()
578 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE; in emc_prepare_timing_change()
579 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
691 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST, in emc_prepare_timing_change()
692 emc->regs + EMC_CFG); in emc_prepare_timing_change()
719 val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST); in emc_prepare_timing_change()
722 emc->emc_cfg |= EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
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H A Dtegra210-emc-cc-r21021.c480 u32 emc_cfg, emc_cfg_o, emc_cfg_update, del, value; in tegra210_emc_r21021_periodic_compensation() local
501 emc_cfg_o = emc_readl(emc, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
502 emc_cfg = emc_cfg_o & ~(EMC_CFG_DYN_SELF_REF | in tegra210_emc_r21021_periodic_compensation()
510 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
565 emc_writel(emc, emc_cfg_o, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
611 u32 emc_auto_cal_config, auto_cal_en, emc_cfg, emc_sel_dpd_ctrl; in tegra210_emc_r21021_set_clock() local
648 emc_readl(emc, EMC_CFG); in tegra210_emc_r21021_set_clock()
665 emc_cfg = next->burst_regs[EMC_CFG_INDEX]; in tegra210_emc_r21021_set_clock()
666 emc_cfg &= ~(EMC_CFG_DYN_SELF_REF | EMC_CFG_DRAM_ACPD | in tegra210_emc_r21021_set_clock()
720 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_set_clock()
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H A Dtegra124-emc.c39 #define EMC_CFG 0xc macro
456 u32 emc_cfg; member
620 val = readl(emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
623 writel(val, emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
705 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; in tegra_emc_prepare_timing_change()
706 emc_ccfifo_writel(emc, val, EMC_CFG); in tegra_emc_prepare_timing_change()
842 if (timing->emc_cfg & EMC_CFG_PWR_MASK) in tegra_emc_complete_timing_change()
843 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
889 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
960 EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg") in load_one_timing_from_dt()
H A Dtegra20-emc.c598 u32 emc_cfg, emc_dbg, emc_fbio, emc_adr_cfg; in emc_setup_hw() local
605 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
611 if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) && in emc_setup_hw()
612 !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) { in emc_setup_hw()
619 emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; in emc_setup_hw()
620 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
H A Dtegra210-emc.h26 #define EMC_CFG 0xc macro
H A Dtegra210-emc-core.c245 EMC_CFG,
/openbmc/linux/arch/arm/mach-tegra/
H A Dsleep-tegra30.S18 #define EMC_CFG 0xc macro
502 ldr r1, [r0, #EMC_CFG]
504 str r1, [r0, #EMC_CFG]
570 ldr r1, [r5, #0x0] @ restore EMC_CFG
571 str r1, [r0, #EMC_CFG]
592 .word TEGRA_EMC_BASE + EMC_CFG @0x0
603 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
611 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
619 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
831 ldr r1, [r0, #EMC_CFG]
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H A Dsleep-tegra20.S23 #define EMC_CFG 0xc macro
238 ldr r1, [r0, #EMC_CFG]
240 str r1, [r0, #EMC_CFG]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra20/
H A Dsdram_param.h92 u32 emc_cfg; member
H A Demc.h16 u32 cfg; /* 0x00: EMC_CFG */
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml104 value of the EMC_CFG register for this set of timings