| /openbmc/smbios-mdr/include/ |
| H A D | cpu.hpp | 8 // http://www.apache.org/licenses/LICENSE-2.0
44 using processor = sdbusplus::server::xyz::openbmc_project::inventory::item::Cpu;
59 {0x05, "Intel 386 processor"},
60 {0x06, "Intel 486 processor"},
65 {0x0b, "Intel Pentium processor"},
66 {0x0c, "Pentium Pro processor"},
67 {0x0d, "Pentium II processor"},
68 {0x0e, "Pentium processor with MMX technology"},
69 {0x0f, "Intel Celeron processor"},
70 {0x10, "Pentium II Xeon processor"},
43 using processor = sdbusplus::server::xyz::openbmc_project::inventory::item::Cpu; global() typedef
[all...] |
| /openbmc/linux/arch/arm/mach-imx/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
14 Support for Freescale MXC/iMX-based family of processors
47 This enables support for Freescale i.MX31 processor
54 This enables support for Freescale i.MX35 processor
66 This enables support for Freescale i.MX1 processor
78 This enables support for Freescale i.MX25 processor
86 This enables support for Freescale i.MX27 processor
92 comment "Cortex-A platforms"
105 This enables support for Freescale i.MX50 processor.
112 This enables support for Freescale i.MX51 processor
[all …]
|
| /openbmc/linux/drivers/eisa/ |
| H A D | eisa.ids | 6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
25 ACE7010 "ACME Multi-Function Board"
39 ACR1711 "AcerFrame 1000 486/33 SYSTEM-2"
41 ACR3211 "AcerFrame 3000MP 486 SYSTEM-1"
[all …]
|
| /openbmc/u-boot/board/freescale/ls1021aqds/ |
| H A D | README | 2 --------
6 ------------------
7 The QorIQ LS1 family, which includes the LS1021A communications processor,
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
[all …]
|
| /openbmc/u-boot/board/intel/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0+
15 Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM
23 mini-ITX form factor containing the Intel Braswell SoC, which has
24 a 64-bit quad-core, single-thread, Intel Atom processor, along with
25 serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe,
32 is built on the Chief River platform with Intel Ivybridge Processor
40 the Intel Atom Processor E6xx populated on the COM Express module
48 This is the Intel Edison Compute Module. It contains a dual core Intel
50 eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers.
56 Arduino-certified development and prototyping boards based on Intel
[all …]
|
| /openbmc/linux/Documentation/arch/arm/ |
| H A D | marvell.rst | 13 ------------
16 - 88F5082
17 - 88F5181 a.k.a Orion-1
18 - 88F5181L a.k.a Orion-VoIP
19 - 88F5182 a.k.a Orion-NAS
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8…
25 - 88F5281 a.k.a Orion-2
[all …]
|
| /openbmc/u-boot/board/freescale/ls1021atwr/ |
| H A D | README | 2 --------
6 ------------------
7 The QorIQ LS1 family, which includes the LS1021A communications processor,
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
[all …]
|
| /openbmc/u-boot/board/freescale/ls1012ardb/ |
| H A D | README | 2 --------
3 QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
5 The LS1012ARDB board supports the QorIQ LS1012A processor and is
6 optimized to support the high-bandwidth DDR3L memory and
7 a full complement of high-speed SerDes ports.
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
15 -----------------------
16 - SERDES Connections, 4 lanes supporting:
17 - PCI Express - 3.0
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | ti,k3-r5f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI K3 R5F processor subsystems
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
[all …]
|
| H A D | ti,omap-remoteproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
[all …]
|
| H A D | xlnx,zynqmp-r5fss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx R5F processor subsystem
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
[all …]
|
| /openbmc/linux/Documentation/staging/ |
| H A D | rpmsg.rst | 2 Remote Processor Messaging (rpmsg) Framework
14 Modern SoCs typically employ heterogeneous remote processor devices in
17 flavor of real-time OS.
19 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.
20 Typically, the dual cortex-A9 is running Linux in a SMP configuration,
25 hardware accelerators, and therefore are often used to offload CPU-intensive
26 multimedia tasks from the main application processor.
28 These remote processors could also be used to control latency-sensitive
34 hardware accessible only by the remote processor, reserving kernel-controlled
35 resources on behalf of the remote processor, etc..).
[all …]
|
| H A D | remoteproc.rst | 2 Remote Processor Framework
8 Modern SoCs typically have heterogeneous remote processor devices in asymmetric
10 of operating system, whether it's Linux or any other flavor of real-time OS.
12 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.
13 In a typical configuration, the dual cortex-A9 is running Linux in a SMP
22 platform-specific remoteproc drivers only need to provide a few low-level
24 (for more information about the virtio-based rpmsg bus and its drivers,
29 existing virtio drivers with remote processor backends at a minimal development
39 Boot a remote processor (i.e. load its firmware, power it on, ...).
41 If the remote processor is already powered on, this function immediately
[all …]
|
| /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | commproc.c | 5 * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's
9 * 8220 Communication Processor Module.
17 * communication processor.
19 * Buffer descriptors must be allocated from the dual ported memory
30 * because we have stack and init data in dual port ram
34 #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
46 gd->arch.dp_alloc_base = CPM_DATAONLY_BASE; in m8560_cpm_reset()
47 gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE; in m8560_cpm_reset()
52 cpm->im_cpm_cp.cpcr = CPM_CR_RST; in m8560_cpm_reset()
56 } while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000); in m8560_cpm_reset()
[all …]
|
| /openbmc/u-boot/board/freescale/p1022ds/ |
| H A D | README | 2 --------
3 P1022ds is a Low End Dual core platform supporting the P1022 processor
4 of QorIQ series. P1022 is an e500 based dual core SOC.
8 -------------------------------
21 'setenv hwconfig 'audclk:12;tdm' --- error !
22 'setenv hwconfig 'audclk:11;tdm' --- error !
23 'setenv hwconfig 'audclk:10' --- error !
|
| /openbmc/u-boot/board/freescale/t208xqds/ |
| H A D | README | 1 The T2080QDS is a high-performance computing evaluation, development and
2 test platform supporting the T2080 QorIQ Power Architecture processor.
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
[all …]
|
| /openbmc/u-boot/doc/SPI/ |
| H A D | README.ti_qspi_flash | 1 QSPI U-Boot support
2 ------------------
4 Host processor is connected to serial flash device via qpsi
6 dual and quad read access to external spi devices. The module
14 -------
16 MLO/u-boot.img will be flashed from SD/MMC to the flash device
21 u-boot.img from flash and execute it from SDRAM.
24 -------
28 2. Dual Mode: use two pins for transfers.
32 -----------------------
[all …]
|
| /openbmc/linux/Documentation/hwmon/ |
| H A D | coretemp.rst | 11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
12 - 0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
13 - 0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield),
14 - 0x26 (Tunnel Creek Atom), 0x27 (Medfield Atom),
15 - 0x36 (Cedar Trail Atom)
19 Intel 64 and IA-32 Architectures Software Developer's Manual
27 -----------
30 inside Intel CPUs. This driver can read both the per-core and per-package
31 temperature using the appropriate sensors. The per-package sensor is new;
40 Temperature known as TjMax is the maximum junction temperature of processor,
[all …]
|
| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | immap_8xx.h | 6 * and the dual port ram for the Communication Processor Module.
10 * functional files.....but anyone else is welcome to try. -- Dan
174 /* The key to unlock registers maintained by keep-alive power.
214 /* Communication Processor Module Interrupt Controller.
247 /* Communication Processor Module Timers
275 /* Finally, the Communication Processor stuff.....
310 uint fec_hash_table_high; /* upper 32-bits of hash table */
311 uint fec_hash_table_low; /* lower 32-bits of hash table */
326 uint fec_r_bound; /* end of RAM (read-only) */
397 /* Port E - MPC87x/88x only.
[all …]
|
| /openbmc/linux/drivers/edac/ |
| H A D | ie31200_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel E3-1200
6 * Support for the E3-1200 processor family. Heavily based on previous
12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/)
14 * 0108: Xeon E3-1200 Processor Family DRAM Controller
15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
[all …]
|
| /openbmc/linux/arch/powerpc/platforms/85xx/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 bool "Freescale Book-E Machine Type"
39 BSC9132 is a heterogeneous SoC containing dual e500v2 powerpc cores
40 and dual StarCore SC3850 DSP cores.
108 Freescale P2020 processor.
144 bool "Freescale TWR-P102x"
147 This option enables support for the TWR-P1025 board.
162 bool "X-ES single-board computer"
165 This option enables support for the various single-board
166 computers from Extreme Engineering Solutions (X-ES) based on
[all …]
|
| /openbmc/linux/sound/soc/sof/xtensa/ |
| H A D | core.c | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
14 #include "../sof-priv.h"
23 * From 4.4.1.5 table 4-64 Exception Causes of Xtensa
30 "Processor internal physical address or data error during instruction fetch"},
32 "Processor internal physical address or data error during load or store"},
34 "Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT register"},
89 dev_printk(level, sdev->dev, "error: DSP Firmware Oops\n"); in xtensa_dsp_oops()
91 if (xtensa_exception_causes[i].id == xoops->exccause) { in xtensa_dsp_oops()
92 dev_printk(level, sdev->dev, in xtensa_dsp_oops()
[all …]
|
| /openbmc/linux/Documentation/gpu/ |
| H A D | komeda-kms.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 The drm/komeda driver supports the Arm display processor D71 and later products,
23 -----
30 ------
39 -------------------
41 frame. its output frame can be fed into post image processor for showing it on
47 --------------------------
51 Post image processor (improc)
52 -----------------------------
53 Post image processor adjusts frame data like gamma and color space to fit the
[all …]
|
| /openbmc/u-boot/board/freescale/t1040qds/ |
| H A D | README | 2 --------
7 ------------------
8 The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
9 processor cores with high-performance data path acceleration architecture
14 - Four e5500 cores, each with a private 256 KB L2 cache
15 - 256 KB shared L3 CoreNet platform cache (CPC)
16 - Interconnect CoreNet platform
17 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
19 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
21 - Packet parsing, classification, and distribution
[all …]
|
| /openbmc/linux/drivers/remoteproc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
5 bool "Support for Remote Processor subsystem"
33 processor framework.
44 processor framework.
54 This can be either built-in or a loadable module.
62 Say y here to support Mediatek's System Companion Processor (SCP) via
63 the remote processor framework.
74 Say y here to support OMAP's remote processors (dual M3
75 and DSP on OMAP4) via the remote processor framework.
80 use-cases to run on your platform (multimedia codecs are
[all …]
|