| /openbmc/linux/drivers/gpu/drm/tegra/ |
| H A D | dpaux.c | 26 #include "dpaux.h"
76 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux, in tegra_dpaux_readl() argument
79 u32 value = readl(dpaux->regs + (offset << 2)); in tegra_dpaux_readl()
81 trace_dpaux_readl(dpaux->dev, offset, value); in tegra_dpaux_readl()
86 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, in tegra_dpaux_writel() argument
89 trace_dpaux_writel(dpaux->dev, offset, value); in tegra_dpaux_writel()
90 writel(value, dpaux->regs + (offset << 2)); in tegra_dpaux_writel()
93 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer, in tegra_dpaux_write_fifo() argument
105 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i)); in tegra_dpaux_write_fifo()
109 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer, in tegra_dpaux_read_fifo() argument
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| H A D | Makefile | 22 dpaux.o \
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| H A D | drm.h | 173 /* from dpaux.c */
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| /openbmc/linux/Documentation/devicetree/bindings/display/tegra/ |
| H A D | nvidia,tegra124-dpaux.yaml | 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
14 The Tegra Display Port Auxiliary (DPAUX) pad controller manages two
15 pins which can be assigned to either the DPAUX channel or to an I2C
18 When configured for DisplayPort AUX operation, the DPAUX controller
24 pattern: "^dpaux@[0-9a-f]+$"
29 - nvidia,tegra124-dpaux
30 - nvidia,tegra210-dpaux
31 - nvidia,tegra186-dpaux
32 - nvidia,tegra194-dpaux
35 - const: nvidia,tegra132-dpaux
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| H A D | nvidia,tegra124-sor.yaml | 99 nvidia,dpaux:
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| /openbmc/u-boot/doc/device-tree-bindings/gpu/ |
| H A D | nvidia,tegra20-host1x.txt | 220 - nvidia,dpaux: phandle to a DispayPort AUX interface
222 - dpaux: DisplayPort AUX interface
223 - compatible: "nvidia,tegra124-dpaux"
229 - dpaux: clock input for the DPAUX hardware
234 - dpaux
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| /openbmc/linux/arch/arm64/boot/dts/nvidia/ |
| H A D | tegra194.dtsi | 2093 dpaux0: dpaux@155c0000 {
2094 compatible = "nvidia,tegra194-dpaux";
2099 clock-names = "dpaux", "parent";
2101 reset-names = "dpaux";
2107 groups = "dpaux-io";
2112 groups = "dpaux-io";
2117 groups = "dpaux-io";
2127 dpaux1: dpaux@155d0000 {
2128 compatible = "nvidia,tegra194-dpaux";
2133 clock-names = "dpaux", "parent";
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| H A D | tegra210.dtsi | 106 dpaux1: dpaux@54040000 {
107 compatible = "nvidia,tegra210-dpaux";
112 clock-names = "dpaux", "parent";
114 reset-names = "dpaux";
119 groups = "dpaux-io";
124 groups = "dpaux-io";
129 groups = "dpaux-io";
340 dpaux: dpaux@545c0000 { label
341 compatible = "nvidia,tegra210-dpaux";
346 clock-names = "dpaux", "parent";
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| H A D | tegra186.dtsi | 1522 dpaux1: dpaux@15040000 {
1523 compatible = "nvidia,tegra186-dpaux";
1528 clock-names = "dpaux", "parent";
1530 reset-names = "dpaux";
1536 groups = "dpaux-io";
1541 groups = "dpaux-io";
1546 groups = "dpaux-io";
1779 dpaux: dpaux@155c0000 { label
1780 compatible = "nvidia,tegra186-dpaux";
1785 clock-names = "dpaux", "parent";
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| H A D | tegra186-p3509-0000+p3636-0001.dts | 792 dpaux@15040000 {
811 nvidia,dpaux = <&dpaux>;
827 dpaux@155c0000 {
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| H A D | tegra132-norrin.dts | 45 nvidia,dpaux = <&dpaux>;
49 dpaux: dpaux@545c0000 { label
1057 ddc-i2c-bus = <&dpaux>;
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| H A D | tegra132.dtsi | 156 dpaux: dpaux@545c0000 { label
157 compatible = "nvidia,tegra124-dpaux";
162 clock-names = "dpaux", "parent";
164 reset-names = "dpaux";
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| H A D | tegra194-p2972-0000.dts | 2142 dpaux@155c0000 {
2146 dpaux@155d0000 {
2150 dpaux@155e0000 {
2161 nvidia,dpaux = <&dpaux0>;
2171 nvidia,dpaux = <&dpaux1>;
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| H A D | tegra210-p3450-0000.dts | 60 dpaux@54040000 {
81 nvidia,dpaux = <&dpaux>;
97 dpaux@545c0000 {
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| H A D | tegra186-p2771-0000.dts | 2439 dpaux@15040000 {
2458 nvidia,dpaux = <&dpaux>;
2473 dpaux@155c0000 {
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| H A D | tegra194-p3509-0000.dtsi | 2182 dpaux@155c0000 {
2186 dpaux@155d0000 {
2197 nvidia,dpaux = <&dpaux0>;
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| H A D | tegra210-smaug.dts | 34 dpaux: dpaux@545c0000 { label
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | tegra210.dtsi | 95 dpaux1: dpaux@54040000 {
96 compatible = "nvidia,tegra210-dpaux";
101 clock-names = "dpaux", "parent";
103 reset-names = "dpaux";
241 dpaux: dpaux@545c0000 { label
242 compatible = "nvidia,tegra124-dpaux";
247 clock-names = "dpaux", "parent";
249 reset-names = "dpaux";
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| H A D | tegra124.dtsi | 153 dpaux: dpaux@545c0000 { label
154 compatible = "nvidia,tegra124-dpaux";
159 clock-names = "dpaux", "parent";
161 reset-names = "dpaux";
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| H A D | tegra124-nyan.dtsi | 31 nvidia,dpaux = <&dpaux>;
35 dpaux@545c0000 {
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| /openbmc/linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra124-nyan-big-fhd.dts | 9 dpaux@545c0000 {
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| H A D | tegra124.dtsi | 195 dpaux: dpaux@545c0000 { label
196 compatible = "nvidia,tegra124-dpaux";
201 clock-names = "dpaux", "parent";
203 reset-names = "dpaux";
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| H A D | tegra124-nyan.dtsi | 55 nvidia,dpaux = <&dpaux>;
59 dpaux@545c0000 {
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| H A D | tegra124-venice2.dts | 44 nvidia,dpaux = <&dpaux>;
48 dpaux@545c0000 {
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| /openbmc/u-boot/drivers/video/tegra124/ |
| H A D | dp.c | 84 debug("dp: DPAUX transaction timeout\n"); in tegra_dpaux_wait_transaction()
1609 { .compatible = "nvidia,tegra124-dpaux" },
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