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/openbmc/openbmc/poky/documentation/tools/
H A Dupdate-documentation-conf87 with open(doc_conf, 'r') as dcf:
88 for line in dcf:
140 with open(doc_conf, 'w') as dcf:
142 dcf.write(line)
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_clk.c56 regs->CLK0_CLK8_CURRENT_CNT = REG_READ(CLK0_CLK8_CURRENT_CNT) / 10; //dcf clk in rv1_dump_clk_registers()
63 regs->CLK0_CLK8_DS_CNTL = REG_READ(CLK0_CLK8_DS_CNTL) / 10; //dcf deep sleep divider in rv1_dump_clk_registers()
65 regs->CLK0_CLK8_ALLOW_DS = REG_READ(CLK0_CLK8_ALLOW_DS); //dcf deep sleep allow in rv1_dump_clk_registers()
H A Drv1_clk_mgr.c247 //DCF Clock in rv1_update_clocks()
259 /* make sure dcf clk is before dpp clk to in rv1_update_clocks()
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-timecard25 DCF adjustments from external DCF signal
43 DCF signal is sent to the DCF module
63 DCF output is from the PHC, in DCF format
283 Description: (RW) The DCF and IRIG output signals are in UTC, while the
/openbmc/linux/drivers/block/drbd/
H A Ddrbd_debugfs.c796 #define DCF(name) do { \ in drbd_debugfs_device_attr() macro
803 DCF(oldest_requests); in drbd_debugfs_device_attr()
804 DCF(act_log_extents); in drbd_debugfs_device_attr()
805 DCF(resync_extents); in drbd_debugfs_device_attr()
806 DCF(data_gen_id); in drbd_debugfs_device_attr()
807 DCF(ed_gen_id); in drbd_debugfs_device_attr()
808 #undef DCF in drbd_debugfs_device_attr()
/openbmc/linux/drivers/net/wireless/ti/wl1251/
H A Dinit.h46 * slot number setting to start transmission at DIFS interval - normal DCF
/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_pp_smu.h121 * when DF is in cstate, dcf clock is further divided down
181 * when DF is in cstate, dcf clock is further divided down
H A Ddm_services_types.h86 (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.c71 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
72 #define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep…
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.c86 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
87 #define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep…
/openbmc/linux/drivers/net/wireless/ath/ath5k/
H A Dqcu.c20 Queue Control Unit, DCF Control Unit Functions
31 * DOC: Queue Control Unit (QCU)/DCF Control Unit (DCU) functions
320 * Set DCF properties for the given transmit queue on DCU
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml44 The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
45 finishes, a DCF interrupt is triggered.
/openbmc/linux/Documentation/fb/
H A Dframebuffer.rst262 < name > DCF HR SH1 SH2 HFL VR SV1 SV2 VFL
280 pixclock = 1000000 / DCF
/openbmc/linux/drivers/net/wireless/intersil/p54/
H A Dp54.h188 /* (e)DCF / QOS state */
H A Dlmac.h544 /* e/v DCF setup */
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c302 /* only pipe 0 is read for voltage and dcf/soc clocks */ in calculate_wm_set_for_vlevel()
/openbmc/linux/drivers/ptp/
H A Dptp_ocp.c847 { .name = "DCF", .value = 6 },
864 { .name = "DCF", .value = 0x0020 },
882 { .name = "DCF", .value = 0x0020 },
3774 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF", in ptp_ocp_summary_show()
3782 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in", in ptp_ocp_summary_show()
3831 sprintf(buf, "DCF"); in ptp_ocp_summary_show()
/openbmc/linux/drivers/platform/x86/
H A Dlg-laptop.c39 #define WMI_METHOD_WMBB "2B4F501A-BD3C-4394-8DCF-00A7D2BC8210"
/openbmc/linux/drivers/net/wireless/ti/wlcore/
H A Dconf.h294 * DCF access */
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c291 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider in rn_dump_clk_registers_internal()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c223 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL); //dcf deep sleep divider in vg_dump_clk_registers_internal()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1786 /* only pipe 0 is read for voltage and dcf/soc clocks */ in dcn20_calculate_wm()
1862 // Accounting for SOC/DCF relationship, we can go as high as in dcn20_update_bounding_box()
2210 /* only pipe 0 is read for voltage and dcf/soc clocks */ in calculate_wm_set_for_vlevel()
/openbmc/linux/tools/testing/selftests/tc-testing/tc-tests/actions/
H A Dmpls.json1091 "id": "3dcf",
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu10_hwmgr.c199 "Attempt to set DCF Clock Failed!", return -EINVAL); in smu10_set_clock_limit()
/openbmc/qemu/hw/usb/
H A Dquirks-ftdi-ids.h258 #define FTDI_ELV_UDF77_PID 0xFB5E /* USB DCF Funkuhr (UDF 77) */

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