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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi3 * Device Tree Source for AM43xx clock data
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
26 sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 {
[all …]
H A Dam33xx-clocks.dtsi3 * Device Tree Source for AM33xx clock data
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
20 clock-output-names = "adc_tsc_fck";
22 clock-mult = <1>;
[all …]
H A Ddra7xx-clocks.dtsi3 * Device Tree Source for DRA7xx clock data
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
22 atl_clkin2_ck: clock-atl-clkin2 {
[all …]
H A Domap3xxx-clocks.dtsi3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
32 #clock-cells = <0>;
33 compatible = "ti,gate-clock";
[all …]
H A Domap54xx-clocks.dtsi3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
[all …]
H A Domap44xx-clocks.dtsi3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
[all …]
H A Domap24xx-clocks.dtsi3 * Device Tree Source for OMAP24xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
31 #clock-cells = <0>;
32 compatible = "ti,composite-clock";
39 #clock-cells = <0>;
[all …]
H A Ddm814x-clocks.dtsi10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
26 clock-names = "clkinp", "clkinpulow";
27 clock-output-names = "481c5080.adpll.dcoclkldo",
33 #clock-cells = <1>;
34 compatible = "ti,dm814-adpll-lj-clock";
[all …]
H A Domap34xx-omap36xx-clocks.dtsi3 * Device Tree Source for OMAP34XX/OMAP36XX clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <1>;
16 clock@a14 {
19 #clock-cells = <2>;
22 aes1_ick: clock-aes1-ick {
23 #clock-cells = <0>;
24 compatible = "ti,omap3-interface-clock";
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
8 clock@a00 {
11 #clock-cells = <2>;
14 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {
15 #clock-cells = <0>;
16 compatible = "ti,composite-no-wait-gate-clock";
17 clock-output-names = "ssi_ssr_gate_fck_3430es2";
23 clock@a40 {
26 #clock-cells = <2>;
29 ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 {
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dam43xx-clocks.dtsi2 * Device Tree Source for AM43xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
20 #clock-cells = <0>;
21 compatible = "ti,mux-clock";
28 #clock-cells = <0>;
29 compatible = "ti,mux-clock";
36 #clock-cells = <0>;
37 compatible = "fixed-factor-clock";
39 clock-mult = <1>;
[all …]
H A Domap3xxx-clocks.dtsi2 * Device Tree Source for OMAP3 clock data
12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <16800000>;
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
25 #clock-cells = <0>;
26 compatible = "ti,divider-clock";
35 #clock-cells = <0>;
36 compatible = "ti,gate-clock";
[all …]
H A Dkeystone-clocks.dtsi2 * Device Tree Source for Keystone 2 clock tree
17 #clock-cells = <0>;
18 compatible = "ti,keystone,pll-mux-clock";
23 clock-output-names = "mainmuxclk";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
30 clock-div = <1>;
31 clock-mult = <1>;
32 clock-output-names = "chipclk1";
36 #clock-cells = <0>;
[all …]
H A Dam33xx-clocks.dtsi2 * Device Tree Source for AM33xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
23 clock-mult = <1>;
24 clock-div = <1>;
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
31 clock-mult = <1>;
[all …]
H A Ddra7xx-clocks.dtsi2 * Device Tree Source for DRA7xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,dra7-atl-clock";
18 #clock-cells = <0>;
19 compatible = "ti,dra7-atl-clock";
24 #clock-cells = <0>;
25 compatible = "ti,dra7-atl-clock";
30 #clock-cells = <0>;
31 compatible = "ti,dra7-atl-clock";
36 #clock-cells = <0>;
[all …]
H A Dkeystone-k2hk-clocks.dtsi4 * Keystone 2 Kepler/Hawking SoC clock nodes
13 #clock-cells = <0>;
14 compatible = "ti,keystone,pll-clock";
16 clock-output-names = "arm-pll-clk";
22 #clock-cells = <0>;
23 compatible = "ti,keystone,main-pll-clock";
30 #clock-cells = <0>;
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "papllclk";
39 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-clocks.dtsi3 * Device Tree Source for Keystone 2 clock tree
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
20 clock-output-names = "mainmuxclk";
24 #clock-cells = <0>;
25 compatible = "fixed-factor-clock";
27 clock-div = <1>;
28 clock-mult = <1>;
29 clock-output-names = "chipclk1";
33 #clock-cells = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
26 containing clock control registers
[all …]
H A Dmvebu-core-clock.txt1 * Core Clock bindings for Marvell MVEBU SoCs
3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
7 The following is a list of provided IDs and clock names on Armada 370/XP:
8 0 = tclk (Internal Bus clock)
9 1 = cpuclk (CPU clock)
10 2 = nbclk (L2 Cache clock)
11 3 = hclk (DRAM control clock)
12 4 = dramclk (DDR clock)
[all …]
H A Dqcom,mmcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller
14 Qualcomm multimedia clock control module provides the clocks, resets and
37 clock-names:
41 '#clock-cells':
55 Protected clock specifier list as per common clock binding
64 - '#clock-cells'
83 - description: PLL 3 clock
84 - description: PLL 3 Vote clock
85 - description: DSI phy instance 1 dsi clock
[all …]
H A Dsamsung,exynos5260-clock.yaml4 $id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
7 title: Samsung Exynos5260 SoC clock controller
18 - "fin_pll" - PLL input clock from XXTI
19 - "xrtcxti" - input clock from XRTCXTI
20 - "ioclk_pcm_extclk" - pcm external operation clock
21 - "ioclk_spdif_extclk" - spdif external operation clock
22 - "ioclk_i2s_cdclk" - i2s0 codec clock
26 are fed into the clock controller and then routed to the hardware blocks.
28 - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
29 - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
[all …]
H A Dtesla,fsd-clock.yaml4 $id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
7 title: Tesla FSD (Full Self-Driving) SoC clock controller
14 FSD clock controller consist of several clock management unit
16 The root clock comes from external OSC clock (24 MHz).
19 'dt-bindings/clock/fsd-clk.h' header.
24 - tesla,fsd-clock-cmu
25 - tesla,fsd-clock-imem
26 - tesla,fsd-clock-peric
27 - tesla,fsd-clock-fsys0
28 - tesla,fsd-clock-fsys1
[all …]
/openbmc/linux/drivers/clk/qcom/
H A DKconfig14 tristate "Support for Qualcomm's clock controllers"
40 tristate "MSM8916 APCS Clock Controller"
43 Support for the APCS Clock Controller on msm8916 devices. The
49 tristate "MSM8996 CPU Clock Controller"
54 Support for the CPU clock controller on msm8996 devices.
55 Say Y if you want to support CPU clock scaling using CPUfreq
59 tristate "SDX55 and SDX65 APCS Clock Controller"
63 Support for the APCS Clock Controller on SDX55, SDX65 platforms. The
69 tristate "RPM based Clock Controller"
76 memory and accepts clock requests, aggregates the requests and turns
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi41 clock-names = "timclk", "apb_pclk";
50 clock-names = "timclk", "apb_pclk";
199 #clock-cells = <0>;
200 compatible = "fixed-clock";
201 clock-frequency = <19200000>;
205 * The 2.4 MHz TIMCLK reference clock is active at
207 * divided by 8. This clock is used by the timers and
211 #clock-cells = <0>;
212 compatible = "fixed-factor-clock";
213 clock-div = <8>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Dgate.txt1 Binding for Texas Instruments gate clock.
5 This binding uses the common clock binding[1]. This clock is
6 quite much similar to the basic gate-clock [2], however,
8 is provided for this clock, the code assumes that a clockdomain
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
14 [3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
18 "ti,gate-clock" - basic gate clock
19 "ti,wait-gate-clock" - gate clock which waits until clock is active before
21 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
[all …]

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