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/openbmc/linux/drivers/target/iscsi/
H A Discsi_target_erl2.c78 struct iscsi_conn_recovery *cr) in iscsit_attach_active_connection_recovery_entry() argument
81 list_add_tail(&cr->cr_list, &sess->cr_active_list); in iscsit_attach_active_connection_recovery_entry()
89 struct iscsi_conn_recovery *cr) in iscsit_attach_inactive_connection_recovery_entry() argument
92 list_add_tail(&cr->cr_list, &sess->cr_inactive_list); in iscsit_attach_inactive_connection_recovery_entry()
106 struct iscsi_conn_recovery *cr; in iscsit_get_inactive_connection_recovery_entry() local
109 list_for_each_entry(cr, &sess->cr_inactive_list, cr_list) { in iscsit_get_inactive_connection_recovery_entry()
110 if (cr->cid == cid) { in iscsit_get_inactive_connection_recovery_entry()
112 return cr; in iscsit_get_inactive_connection_recovery_entry()
123 struct iscsi_conn_recovery *cr, *cr_tmp; in iscsit_free_connection_recovery_entries() local
126 list_for_each_entry_safe(cr, cr_tmp, &sess->cr_active_list, cr_list) { in iscsit_free_connection_recovery_entries()
[all …]
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_pci_id_tbl.h98 CH_PCI_ID_TABLE_FENTRY(0x4001), /* T420-cr */
99 CH_PCI_ID_TABLE_FENTRY(0x4002), /* T422-cr */
100 CH_PCI_ID_TABLE_FENTRY(0x4003), /* T440-cr */
110 CH_PCI_ID_TABLE_FENTRY(0x400d), /* T480-cr */
111 CH_PCI_ID_TABLE_FENTRY(0x400e), /* T440-LP-cr */
112 CH_PCI_ID_TABLE_FENTRY(0x4080), /* Custom T480-cr */
113 CH_PCI_ID_TABLE_FENTRY(0x4081), /* Custom T440-cr */
114 CH_PCI_ID_TABLE_FENTRY(0x4082), /* Custom T420-cr */
116 CH_PCI_ID_TABLE_FENTRY(0x4084), /* Custom T440-cr */
117 CH_PCI_ID_TABLE_FENTRY(0x4085), /* Custom T420-cr */
[all …]
/openbmc/u-boot/arch/arm/mach-imx/
H A Dddrmc-vf610.c119 writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); in ddrmc_ctrl_init_ddr3()
120 writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]); in ddrmc_ctrl_init_ddr3()
121 writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]); in ddrmc_ctrl_init_ddr3()
123 writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]); in ddrmc_ctrl_init_ddr3()
125 DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]); in ddrmc_ctrl_init_ddr3()
129 &ddrmr->cr[13]); in ddrmc_ctrl_init_ddr3()
132 DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]); in ddrmc_ctrl_init_ddr3()
134 DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]); in ddrmc_ctrl_init_ddr3()
136 DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]); in ddrmc_ctrl_init_ddr3()
138 DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]); in ddrmc_ctrl_init_ddr3()
[all …]
H A Dddrmc-vf610-calibration.c110 while (!(readl(&ddrmr->cr[94]) & DDRMC_CR94_SWLVL_OP_DONE))
113 do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_LOAD, \
117 do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_START, \
121 do { clrsetbits_le32(&ddrmr->cr[94], DDRMC_CR94_SWLVL_EXIT, \
144 (readl(&ddrmr->cr[105]) >> DDRMC_CR105_RDLVL_DL_0_OFF) & 0xFFFF; in ddrmc_cal_dqs_to_dq()
145 u16 rdlvl_dl_1_def = readl(&ddrmr->cr[110]) & 0xFFFF; in ddrmc_cal_dqs_to_dq()
158 writel(0x40703030, &ddrmr->cr[144]); in ddrmc_cal_dqs_to_dq()
159 writel(0x40, &ddrmr->cr[145]); in ddrmc_cal_dqs_to_dq()
160 writel(0x40, &ddrmr->cr[146]); in ddrmc_cal_dqs_to_dq()
162 tmp = readl(&ddrmr->cr[144]); in ddrmc_cal_dqs_to_dq()
[all …]
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-yuv-planar.rst14 Cb and Cr components interleaved.
16 - Fully planar formats use three planes to store the Y, Cb and Cr components
36 components in the second plane. The Cb and Cr components are interleaved in the
37 chroma plane, with Cb and Cr always stored in pairs. The chroma order is
72 - Cb, Cr
79 - Cr, Cb
86 - Cb, Cr
93 - Cr, Cb
100 - Cb, Cr
109 - Cb, Cr
[all …]
H A Dpixfmt-packed-yuv.rst10 Cr components consecutively in memory. They may apply subsampling to the chroma
16 - 'Y', 'Cb' and 'Cr' denote bits of the luma, blue chroma (also known as
26 full triplet of Y, Cb and Cr values.
29 component. They are named based on the order of the Y, Cb and Cr components as
33 Cb\ :sub:`5-0` Cr\ :sub:`4-0`], and stored in memory in two bytes,
34 [Cb\ :sub:`2-0` Cr\ :sub:`4-0`] followed by [Y'\ :sub:`4-0` Cb\ :sub:`5-3`].
84 - Cr\ :sub:`3`
85 - Cr\ :sub:`2`
86 - Cr\ :sub:`1`
87 - Cr\ :sub:`0`
[all …]
H A Dpixfmt-uv8.rst30 - Cr\ :sub:`00`
32 - Cr\ :sub:`01`
35 - Cr\ :sub:`10`
37 - Cr\ :sub:`11`
40 - Cr\ :sub:`20`
42 - Cr\ :sub:`21`
45 - Cr\ :sub:`30`
47 - Cr\ :sub:`31`
/openbmc/qemu/target/hppa/
H A Dgdbstub.c43 val = env->cr[CR_SAR]; in hppa_cpu_gdb_read_register()
58 val = env->cr[CR_EIEM]; in hppa_cpu_gdb_read_register()
61 val = env->cr[CR_IIR]; in hppa_cpu_gdb_read_register()
64 val = env->cr[CR_ISR]; in hppa_cpu_gdb_read_register()
67 val = env->cr[CR_IOR]; in hppa_cpu_gdb_read_register()
70 val = env->cr[CR_IPSW]; in hppa_cpu_gdb_read_register()
97 val = env->cr[CR_RC]; in hppa_cpu_gdb_read_register()
100 val = env->cr[CR_PID1]; in hppa_cpu_gdb_read_register()
103 val = env->cr[CR_PID2]; in hppa_cpu_gdb_read_register()
106 val = env->cr[CR_SCRCCR]; in hppa_cpu_gdb_read_register()
[all …]
/openbmc/linux/drivers/crypto/ccp/
H A Dccp-dev-v3.c74 static int ccp_do_cmd(struct ccp_op *op, u32 *cr, unsigned int cr_count) in ccp_do_cmd() argument
107 iowrite32(*(cr + i), cr_addr); in ccp_do_cmd()
150 u32 cr[6]; in ccp_perform_aes() local
153 cr[0] = (CCP_ENGINE_AES << REQ1_ENGINE_SHIFT) in ccp_perform_aes()
158 cr[1] = op->src.u.dma.length - 1; in ccp_perform_aes()
159 cr[2] = ccp_addr_lo(&op->src.u.dma); in ccp_perform_aes()
160 cr[3] = (op->sb_ctx << REQ4_KSB_SHIFT) in ccp_perform_aes()
163 cr[4] = ccp_addr_lo(&op->dst.u.dma); in ccp_perform_aes()
164 cr[5] = (CCP_MEMTYPE_SYSTEM << REQ6_MEMTYPE_SHIFT) in ccp_perform_aes()
168 cr[0] |= ((0x7f) << REQ1_AES_CFB_SIZE_SHIFT); in ccp_perform_aes()
[all …]
/openbmc/linux/arch/csky/abiv2/inc/abi/
H A Dckmmu.h11 return mfcr("cr<0, 15>"); in read_mmu_index()
16 mtcr("cr<0, 15>", value); in write_mmu_index()
21 return mfcr("cr<2, 15>"); in read_mmu_entrylo0()
26 return mfcr("cr<3, 15>"); in read_mmu_entrylo1()
31 mtcr("cr<6, 15>", value); in write_mmu_pagemask()
36 return mfcr("cr<4, 15>"); in read_mmu_entryhi()
41 mtcr("cr<4, 15>", value); in write_mmu_entryhi()
46 return mfcr("cr<30, 15>"); in read_mmu_msa0()
51 mtcr("cr<30, 15>", value); in write_mmu_msa0()
56 return mfcr("cr<31, 15>"); in read_mmu_msa1()
[all …]
H A Dentry.h21 #define usp cr<14, 1>
209 mfcr \rx, cr<0, 15>
213 mfcr \rx, cr<4, 15>
217 mfcr \rx, cr<8, 15>
221 mfcr \rx, cr<29, 15>
225 mfcr \rx, cr<28, 15>
229 mtcr \rx, cr<4, 15>
233 mtcr \rx, cr<8, 15>
237 #define MSA_SET cr<30, 15>
238 #define MSA_CLR cr<31, 15>
[all …]
/openbmc/u-boot/arch/arm/mach-at91/
H A Dmpddrc.c24 static int ddr2_decodtype_is_seq(const unsigned int base, u32 cr) in ddr2_decodtype_is_seq() argument
30 (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)) in ddr2_decodtype_is_seq()
43 u32 ba_off, cr; in ddr2_init() local
46 ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; in ddr2_init()
47 if (ddr2_decodtype_is_seq(base, mpddr_value->cr)) in ddr2_init()
48 ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; in ddr2_init()
56 writel(mpddr_value->cr, &mpddr->cr); in ddr2_init()
91 cr = readl(&mpddr->cr); in ddr2_init()
92 writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr); in ddr2_init()
105 cr = readl(&mpddr->cr); in ddr2_init()
[all …]
/openbmc/linux/fs/xfs/scrub/
H A Drmap.c194 struct xchk_rmap *cr, in xchk_rmapbt_check_overlapping() argument
203 if (cr->overlap_rec.rm_blockcount == 0) in xchk_rmapbt_check_overlapping()
207 pnext = cr->overlap_rec.rm_startblock + cr->overlap_rec.rm_blockcount; in xchk_rmapbt_check_overlapping()
212 if (!xchk_rmapbt_is_shareable(bs->sc, &cr->overlap_rec) || in xchk_rmapbt_check_overlapping()
222 memcpy(&cr->overlap_rec, irec, sizeof(struct xfs_rmap_irec)); in xchk_rmapbt_check_overlapping()
228 struct xchk_rmap *cr, in xchk_rmap_mergeable() argument
231 const struct xfs_rmap_irec *r1 = &cr->prev_rec; in xchk_rmap_mergeable()
234 if (cr->prev_rec.rm_blockcount == 0) in xchk_rmap_mergeable()
258 struct xchk_rmap *cr, in xchk_rmapbt_check_mergeable() argument
264 if (xchk_rmap_mergeable(cr, irec)) in xchk_rmapbt_check_mergeable()
[all …]
/openbmc/linux/arch/ia64/include/asm/native/
H A Dinst.h12 mov reg = cr.ifa
15 mov reg = cr.itir
18 mov reg = cr.isr
21 mov reg = cr.iha
24 (pred) mov reg = cr.ipsr
27 mov reg = cr.iim
30 mov reg = cr.iip
33 mov reg = cr.ivr
42 mov cr.ifa = reg
45 (pred) mov cr.itir = reg
[all …]
/openbmc/linux/drivers/misc/cxl/
H A Dsysfs.c508 int cr; member
519 struct afu_config_record *cr = to_cr(kobj); in vendor_show() local
521 return scnprintf(buf, PAGE_SIZE, "0x%.4x\n", cr->vendor); in vendor_show()
527 struct afu_config_record *cr = to_cr(kobj); in device_show() local
529 return scnprintf(buf, PAGE_SIZE, "0x%.4x\n", cr->device); in device_show()
535 struct afu_config_record *cr = to_cr(kobj); in class_show() local
537 return scnprintf(buf, PAGE_SIZE, "0x%.6x\n", cr->class); in class_show()
544 struct afu_config_record *cr = to_cr(kobj); in afu_read_config() local
550 rc = cxl_ops->afu_cr_read64(afu, cr->cr, off & ~0x7, &val); in afu_read_config()
577 struct afu_config_record *cr = to_cr(kobj); in release_afu_config_record() local
[all …]
/openbmc/linux/net/wireless/
H A Dsme.c276 struct cfg80211_connect_resp_params cr; in cfg80211_conn_work() local
278 memset(&cr, 0, sizeof(cr)); in cfg80211_conn_work()
279 cr.status = -1; in cfg80211_conn_work()
280 cr.links[0].bssid = bssid; in cfg80211_conn_work()
281 cr.timeout_reason = treason; in cfg80211_conn_work()
282 __cfg80211_connect_result(wdev->netdev, &cr, false); in cfg80211_conn_work()
391 struct cfg80211_connect_resp_params cr; in cfg80211_sme_rx_auth() local
393 memset(&cr, 0, sizeof(cr)); in cfg80211_sme_rx_auth()
394 cr.status = status_code; in cfg80211_sme_rx_auth()
395 cr.links[0].bssid = mgmt->bssid; in cfg80211_sme_rx_auth()
[all …]
/openbmc/linux/arch/s390/include/asm/
H A Dctl_reg.h59 static __always_inline void __ctl_set_bit(unsigned int cr, unsigned int bit) in __ctl_set_bit() argument
63 __ctl_store(reg, cr, cr); in __ctl_set_bit()
65 __ctl_load(reg, cr, cr); in __ctl_set_bit()
68 static __always_inline void __ctl_clear_bit(unsigned int cr, unsigned int bit) in __ctl_clear_bit() argument
72 __ctl_store(reg, cr, cr); in __ctl_clear_bit()
74 __ctl_load(reg, cr, cr); in __ctl_clear_bit()
77 void smp_ctl_set_clear_bit(int cr, int bit, bool set);
79 static inline void ctl_set_bit(int cr, int bit) in ctl_set_bit() argument
81 smp_ctl_set_clear_bit(cr, bit, true); in ctl_set_bit()
84 static inline void ctl_clear_bit(int cr, int bit) in ctl_clear_bit() argument
[all …]
/openbmc/qemu/hw/timer/
H A Dimx_epit.c40 return "CR"; in imx_epit_reg_name()
70 if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { in imx_epit_update_int()
79 uint32_t clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); in imx_epit_get_freq()
80 uint32_t prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS); in imx_epit_get_freq()
94 s->cr = 0; in imx_epit_reset()
96 s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); in imx_epit_reset()
105 * The reset switches off the input clock, so even if the CR.EN is still in imx_epit_reset()
125 reg_value = s->cr; in imx_epit_read()
168 bool is_active = (s->cr & CR_EN) && imx_epit_get_freq(s); in imx_epit_update_compare_timer()
207 * of CR.OCIEN bit, as this bit affects interrupt generation only. The in imx_epit_update_compare_timer()
[all …]
/openbmc/linux/arch/parisc/include/asm/
H A Dspecial_insns.h40 unsigned long cr; \
43 "=r" (cr) : "i" (reg) \
45 cr; \
48 #define mtctl(gr, cr) \ argument
51 : "r" (gr), "i" (cr) : "memory")
57 unsigned long cr; \
60 : "=r" (cr) : "i"(reg) \
62 cr; \
65 #define mtsp(val, cr) \ argument
67 __asm__ __volatile__("mtsp %%r0,%0" : : "i" (cr) : "memory"); \
[all …]
/openbmc/linux/drivers/gpu/drm/mcde/
H A Dmcde_clk_div.c13 u32 cr; member
24 val = readl(mcde->regs + cdiv->cr); in mcde_clk_div_enable()
38 writel(val, mcde->regs + cdiv->cr); in mcde_clk_div_enable()
87 u32 cr; in mcde_clk_div_recalc_rate() local
98 cr = readl(mcde->regs + cdiv->cr); in mcde_clk_div_recalc_rate()
99 if (cr & MCDE_CRX1_BCD) in mcde_clk_div_recalc_rate()
103 div = cr & MCDE_CRX1_PCD_MASK; in mcde_clk_div_recalc_rate()
114 u32 cr = 0; in mcde_clk_div_set_rate() local
117 * We cache the CR bits to set the divide in the state so that in mcde_clk_div_set_rate()
122 cr |= MCDE_CRX1_BCD; in mcde_clk_div_set_rate()
[all …]
/openbmc/linux/arch/parisc/kernel/
H A Dtoc.c22 regs->gr[0] = (unsigned long)toc->cr[22]; in toc20_to_pt_regs()
30 regs->iasq[0] = (unsigned long)toc->cr[17]; in toc20_to_pt_regs()
32 regs->iaoq[0] = (unsigned long)toc->cr[18]; in toc20_to_pt_regs()
35 regs->sar = (unsigned long)toc->cr[11]; in toc20_to_pt_regs()
36 regs->iir = (unsigned long)toc->cr[19]; in toc20_to_pt_regs()
37 regs->isr = (unsigned long)toc->cr[20]; in toc20_to_pt_regs()
38 regs->ior = (unsigned long)toc->cr[21]; in toc20_to_pt_regs()
45 regs->gr[0] = toc->cr[22]; in toc11_to_pt_regs()
53 regs->iasq[0] = toc->cr[17]; in toc11_to_pt_regs()
55 regs->iaoq[0] = toc->cr[18]; in toc11_to_pt_regs()
[all …]
/openbmc/linux/drivers/clocksource/
H A Dtimer-fttmr010.c146 u32 cr; in fttmr010_timer_set_next_event() local
159 cr = readl(fttmr010->base + TIMER1_COUNT); in fttmr010_timer_set_next_event()
160 writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); in fttmr010_timer_set_next_event()
164 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
165 cr |= fttmr010->t1_enable_val; in fttmr010_timer_set_next_event()
166 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
184 u32 cr; in fttmr010_timer_shutdown() local
187 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_shutdown()
188 cr &= ~fttmr010->t1_enable_val; in fttmr010_timer_shutdown()
189 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_shutdown()
[all …]
/openbmc/linux/drivers/net/ethernet/ni/
H A Dnixge.c287 u32 cr; in nixge_hw_dma_bd_init() local
344 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_hw_dma_bd_init()
346 cr = ((cr & ~XAXIDMA_COALESCE_MASK) | in nixge_hw_dma_bd_init()
349 cr = ((cr & ~XAXIDMA_DELAY_MASK) | in nixge_hw_dma_bd_init()
352 cr |= XAXIDMA_IRQ_ALL_MASK; in nixge_hw_dma_bd_init()
354 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr); in nixge_hw_dma_bd_init()
357 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_hw_dma_bd_init()
359 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) | in nixge_hw_dma_bd_init()
362 cr = (((cr & ~XAXIDMA_DELAY_MASK)) | in nixge_hw_dma_bd_init()
365 cr |= XAXIDMA_IRQ_ALL_MASK; in nixge_hw_dma_bd_init()
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-iop3xx.c67 u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE; in iop3xx_i2c_enable() local
81 /* NB SR bits not same position as CR IE bits :-( */ in iop3xx_i2c_enable()
86 cr |= IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE | in iop3xx_i2c_enable()
89 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_enable()
95 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_transaction_cleanup() local
97 cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE | in iop3xx_i2c_transaction_cleanup()
100 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_transaction_cleanup()
233 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_send_target_addr() local
246 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK); in iop3xx_i2c_send_target_addr()
247 cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE; in iop3xx_i2c_send_target_addr()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dmpc8536_serdes.c114 /* CR 0 */ in fsl_serdes_init()
121 /* CR 1 */ in fsl_serdes_init()
126 /* CR 2 */ in fsl_serdes_init()
133 /* CR 3 */ in fsl_serdes_init()
142 /* CR 0 */ in fsl_serdes_init()
147 /* CR 1 */ in fsl_serdes_init()
152 /* CR 2 */ in fsl_serdes_init()
157 /* CR 3 */ in fsl_serdes_init()
164 /* CR 0 */ in fsl_serdes_init()
171 /* CR 1 */ in fsl_serdes_init()
[all …]

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