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/openbmc/qemu/hw/timer/
H A Drenesas_cmt.c54 static void update_events(RCMTState *cmt, int ch) in update_events() argument
58 if ((cmt->cmstr & (1 << ch)) == 0) { in update_events()
62 next_time = cmt->cmcor[ch] - cmt->cmcnt[ch]; in update_events()
64 next_time /= cmt->input_freq; in update_events()
72 next_time *= 1 << (3 + FIELD_EX16(cmt->cmcr[ch], CMCR, CKS) * 2); in update_events()
74 timer_mod(&cmt->timer[ch], next_time); in update_events()
77 static int64_t read_cmcnt(RCMTState *cmt, int ch) in read_cmcnt() argument
81 if (cmt->cmstr & (1 << ch)) { in read_cmcnt()
82 delta = (now - cmt->tick[ch]); in read_cmcnt()
84 delta /= cmt->input_freq; in read_cmcnt()
[all …]
/openbmc/linux/drivers/clocksource/
H A Dsh_cmt.c3 * SuperH Timer Support - CMT
35 * The CMT comes in 5 different identified flavours, depending not only on the
52 * registers block address. Some CMT instances have a subset of channels
60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
91 struct sh_cmt_device *cmt; member
244 return ch->cmt->info->read_control(ch->iostart, 0); in sh_cmt_read_cmstr()
246 return ch->cmt->info->read_control(ch->cmt->mapbase, 0); in sh_cmt_read_cmstr()
255 ch->cmt->info->write_control(ch->iostart, 0, value); in sh_cmt_write_cmstr()
256 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmstr()
258 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); in sh_cmt_write_cmstr()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,cmt.yaml4 $id: http://devicetree.org/schemas/timer/renesas,cmt.yaml#
7 title: Renesas Compare Match Timer (CMT)
14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
18 are independent. A particular CMT instance can implement only a subset of the
19 channels supported by the CMT model. Channel indices represent the hardware
20 position of the channel in the CMT and don't match the channel numbers in the
87 - renesas,r8a774a1-cmt1 # 48-bit CMT on RZ/G2M
88 - renesas,r8a774b1-cmt1 # 48-bit CMT on RZ/G2N
89 - renesas,r8a774c0-cmt1 # 48-bit CMT on RZ/G2E
90 - renesas,r8a774e1-cmt1 # 48-bit CMT on RZ/G2H
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/openbmc/u-boot/scripts/
H A Dobjdiff54 echo $TMPD/$CMT${dir#$SRCTREE}
76 CMT="`git rev-parse --short HEAD`"
133 CMT="`git rev-parse --short $1`"
135 if [ -d "$TMPD/$CMT" ]; then
136 rm -rf $TMPD/$CMT
138 echo >&2 "$CMT not found"
/openbmc/linux/scripts/
H A Dobjdiff54 echo $TMPD/$CMT${dir#$SRCTREE}
76 CMT="`git rev-parse --short HEAD`"
133 CMT="`git rev-parse --short $1`"
135 if [ -d "$TMPD/$CMT" ]; then
136 rm -rf $TMPD/$CMT
138 echo >&2 "$CMT not found"
/openbmc/linux/arch/sparc/include/uapi/asm/
H A Dasi.h143 * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates
179 #define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */
180 #define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */
181 #define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */
182 #define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */
183 #define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */
184 #define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */
185 #define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */
186 #define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */
187 #define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */
[all …]
/openbmc/qemu/target/sparc/
H A Dasi.h142 * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates
190 #define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */
191 #define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */
192 #define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */
193 #define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */
194 #define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */
195 #define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */
196 #define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */
197 #define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */
198 #define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */
[all …]
H A Dcpu-feature.h.inc8 FEATURE(CMT)
/openbmc/linux/tools/testing/selftests/resctrl/
H A Dcache.c110 * For CMT,
272 * @cache_span: cache span in bytes for CMT or in lines for CAT
277 * @cmt: CMT test or CAT test
284 bool platform, bool cmt) in show_cache_info() argument
296 (cmt ? (abs(avg_diff) > max_diff) : true); in show_cache_info()
304 ksft_print_msg("Cache span (%s): %zu\n", cmt ? "bytes" : "lines", in show_cache_info()
H A Dresctrl_tests.c53 printf("\t-b benchmark_cmd [options]: run specified benchmark for MBM, MBA and CMT\n"); in cmd_help()
56 printf("e.g. -t mbm,mba,cmt,cat\n"); in cmd_help()
151 ksft_print_msg("Starting CMT test ...\n"); in run_cmt_test()
160 ksft_test_result_skip("Hardware does not support CMT or CMT is disabled\n"); in run_cmt_test()
165 ksft_test_result(!res, "CMT: test\n"); in run_cmt_test()
167 …ksft_print_msg("Intel CMT may be inaccurate when Sub-NUMA Clustering is enabled. Check BIOS config… in run_cmt_test()
H A DREADME74 …-b benchmark_cmd [options]: run specified benchmark for MBM, MBA and CMT default benchmark is buil…
75 -t test list: run tests specified in the test list, e.g. -t mbm,mba,cmt,cat
H A Dresctrl.h71 #define CMT_STR "cmt"
117 bool platform, bool cmt);
/openbmc/qemu/hw/rx/
H A Drx62n.c180 SysBusDevice *cmt; in register_cmt() local
183 object_initialize_child(OBJECT(s), "cmt[*]", in register_cmt()
184 &s->cmt[unit], TYPE_RENESAS_CMT); in register_cmt()
185 cmt = SYS_BUS_DEVICE(&s->cmt[unit]); in register_cmt()
186 qdev_prop_set_uint64(DEVICE(cmt), "input-freq", s->pclk_freq_hz); in register_cmt()
187 sysbus_realize(cmt, &error_abort); in register_cmt()
191 sysbus_connect_irq(cmt, i, in register_cmt()
194 sysbus_mmio_map(cmt, 0, RX62N_CMT_BASE + unit * 0x10); in register_cmt()
/openbmc/linux/Documentation/arch/x86/
H A Dtopology.rst96 are SMT- or CMT-type threads.
98 AMDs nomenclature for a CMT core is "Compute Unit". The kernel always uses
116 AMDs nomenclature for CMT threads is "Compute Unit Core". The kernel always
183 AMD nomenclature for CMT systems::
224 AMD nomenclature for CMT systems::
/openbmc/linux/drivers/hsi/clients/
H A Dnokia-modem.c45 dev_info(modem->device, "CMT rst line change detected\n"); in do_nokia_modem_rst_ind_tasklet()
198 cmtspeech.name = "cmt-speech"; in nokia_modem_probe()
206 dev_err(dev, "Could not register cmt-speech device\n"); in nokia_modem_probe()
213 dev_dbg(dev, "Missing cmt-speech driver\n"); in nokia_modem_probe()
217 dev_err(dev, "Could not load cmt-speech driver (%d)\n", err); in nokia_modem_probe()
H A DKconfig18 tristate "CMT speech"
21 If you say Y here, you will enable the CMT speech protocol used
H A Dssi_protocol.c289 /* CMT speech workaround */ in ssip_set_rxstate()
429 dev_err(&cl->device, "CMT %s\n", (ssi->main_state == ACTIVE) ? in ssip_dump_state()
469 * Workaround for cmt-speech in that case in ssip_keep_alive()
661 /* Workaroud: Ignore CMT Loader message leftover */ in ssip_rx_bootinforeq()
742 dev_dbg(&cl->device, "CMT is ONLINE\n"); in ssip_rx_waketest()
1002 dev_dbg(&cl->device, "Dropping tx data: CMT is OFFLINE\n"); in ssip_pn_xmit()
1017 /* Needed for cmt-speech workaround */ in ssip_pn_xmit()
1039 /* CMT reset event handler */
1043 dev_err(&ssi->cl->device, "CMT reset detected!\n"); in ssip_reset_event()
/openbmc/linux/arch/sh/kernel/cpu/
H A Dclock-cpg.c65 clk_add_alias("fck", "sh-cmt-16.0", "peripheral_clk", NULL); in cpg_clk_init()
66 clk_add_alias("fck", "sh-cmt-32.0", "peripheral_clk", NULL); in cpg_clk_init()
/openbmc/linux/arch/sh/kernel/cpu/sh3/
H A Dsetup-sh7720.c159 .name = "sh-cmt-32",
228 ADC, DMAC2, USBFI, CMT, enumerator
262 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60),
272 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7366.c184 .name = "sh-cmt-32",
265 SDHI, CMT, TSIF, SIU, enumerator
298 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
336 { 0, 0, 0, CMT, 0, USB, } },
351 { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } },
H A Dsetup-sh7343.c234 .name = "sh-cmt-32",
323 IRDA, SDHI, CMT, TSIF, SIU, enumerator
360 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
399 { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
412 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
H A Dsetup-sh7780.c305 HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC, enumerator
328 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
359 PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
369 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
/openbmc/linux/arch/sh/kernel/cpu/sh4/
H A Dsetup-sh7760.c35 MFI, ADC, CMT, enumerator
71 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
100 0, MFI, 0, 0, 0, 0, ADC, CMT, } },
114 MFI, 0, ADC, CMT } },
/openbmc/linux/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7264.c95 [MSTP72] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 2, 0), /* CMT */
124 CLKDEV_ICK_ID("fck", "sh-cmt-16.0", &mstp_clks[MSTP72]),
/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7269.h20 /* Timer(CMT) */

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