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/openbmc/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs.rst5 MIPI CCS camera sensor driver
8 The MIPI CCS camera sensor driver is a generic driver for `MIPI CCS
59 CCS static data
62 The MIPI CCS driver supports CCS static data for all compliant devices,
63 including not just those compliant with CCS 1.1 but also CCS 1.0 and SMIA(++).
64 For CCS the file names are formed as
66 ccs/ccs-sensor-vvvv-mmmm-rrrr.fw (sensor) and
67 ccs/ccs-module-vvvv-mmmm-rrrr.fw (module).
71 ccs/smiapp-sensor-vv-mmmm-rr.fw (sensor) and
72 ccs/smiapp-module-vv-mmmm-rrrr.fw (module).
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H A Dmk-ccs-regs8 my $ccsregs = "ccs-regs.asc";
28 $0 - Create CCS register definitions for C
30 usage: $0 -c ccs-regs.asc -e header -r regarray -l limit-c -L limit-header [-k]
32 -c ccs register file
44 ? '#include "ccs-os.h"' . "\n"
121 #include "ccs-extra.h"
122 #include "ccs-regs.h"
153 #include "ccs-limits.h"
154 #include "ccs-regs.h"
/openbmc/linux/drivers/media/i2c/ccs/
H A DMakefile2 ccs-objs += ccs-core.o ccs-reg-access.o \
3 ccs-quirk.o ccs-limits.o ccs-data.o
4 obj-$(CONFIG_VIDEO_CCS) += ccs.o
H A Dccs-data.h3 * CCS static data in-memory data structure definitions
16 * struct ccs_data_block_version - CCS static data version
32 * struct ccs_reg - CCS register value
44 * struct ccs_if_rule - CCS static data if rule
56 * struct ccs_frame_format_desc - CCS frame format descriptor
66 * struct ccs_frame_format_descs - A series of CCS frame format descriptors
80 * struct ccs_pdaf_readout - CCS PDAF data readout descriptor
90 * struct ccs_rule - A CCS static data rule
182 * struct ccs_data_container - In-memory CCS static data
183 * @version: CCS static data version
H A Dccs.h3 * drivers/media/i2c/smiapp/ccs.h
5 * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
19 #include "ccs-data.h"
20 #include "ccs-limits.h"
21 #include "ccs-quirk.h"
22 #include "ccs-regs.h"
23 #include "ccs-reg-access.h"
24 #include "../ccs-pll.h"
49 #define CCS_NAME "ccs"
H A Dccs-reg-access.h3 * include/media/ccs/ccs-reg-access.h
5 * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
18 #include "ccs-regs.h"
H A DKconfig3 tristate "MIPI CCS/SMIA++/SMIA sensor support"
7 This is a generic driver for MIPI CCS, SMIA++ and SMIA compliant
H A Dccs-quirk.c3 * drivers/media/i2c/ccs/ccs-quirk.c
5 * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
14 #include "ccs.h"
15 #include "ccs-limits.h"
H A Dccs-quirk.h3 * drivers/media/i2c/ccs/ccs-quirk.h
5 * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
/openbmc/linux/drivers/media/i2c/
H A Dccs-pll.h3 * drivers/media/i2c/ccs-pll.h
5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
25 /* CCS PLL flags */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
54 * struct ccs_pll_branch_bk - CCS PLL configuration (back)
56 * A single branch back-end of the CCS PLL tree.
71 * struct ccs_pll - Full CCS PLL configuration
73 * All information required to calculate CCS PLL configuration.
127 * struct ccs_pll_branch_limits_fr - CCS PLL front-end limits
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/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dmipi-ccs.yaml5 $id: http://devicetree.org/schemas/media/i2c/mipi-ccs.yaml#
8 title: MIPI CCS, SMIA++ and SMIA compliant camera sensors
15 CCS (Camera Command Set) is a raw Bayer camera sensor standard defined by the
30 - const: mipi-ccs-1.1
31 - const: mipi-ccs
33 - const: mipi-ccs-1.0
34 - const: mipi-ccs
116 compatible = "mipi-ccs-1.0", "mipi-ccs";
/openbmc/linux/drivers/gpu/drm/ci/
H A Dtestlist.txt368 kms_ccs@pipe-A-random-ccs-data-y_tiled_ccs
369 kms_ccs@pipe-A-random-ccs-data-yf_tiled_ccs
370 kms_ccs@pipe-A-random-ccs-data-y_tiled_gen12_rc_ccs
371 kms_ccs@pipe-A-random-ccs-data-y_tiled_gen12_rc_ccs_cc
372 kms_ccs@pipe-A-random-ccs-data-y_tiled_gen12_mc_ccs
373 kms_ccs@pipe-A-random-ccs-data-4_tiled_dg2_rc_ccs
374 kms_ccs@pipe-A-random-ccs-data-4_tiled_dg2_mc_ccs
375 kms_ccs@pipe-A-random-ccs-data-4_tiled_dg2_rc_ccs_cc
376 kms_ccs@pipe-A-random-ccs-data-4_tiled_mtl_rc_ccs
377 kms_ccs@pipe-A-random-ccs-data-4_tiled_mtl_mc_ccs
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/openbmc/qemu/target/ppc/
H A Dtimebase_helper.c64 CPUState *ccs; in helper_store_purr() local
71 THREAD_SIBLING_FOREACH(cs, ccs) { in helper_store_purr()
72 CPUPPCState *cenv = &POWERPC_CPU(ccs)->env; in helper_store_purr()
82 CPUState *ccs; in helper_store_tbl() local
89 THREAD_SIBLING_FOREACH(cs, ccs) { in helper_store_tbl()
90 CPUPPCState *cenv = &POWERPC_CPU(ccs)->env; in helper_store_tbl()
98 CPUState *ccs; in helper_store_tbu() local
105 THREAD_SIBLING_FOREACH(cs, ccs) { in helper_store_tbu()
106 CPUPPCState *cenv = &POWERPC_CPU(ccs)->env; in helper_store_tbu()
139 CPUState *ccs; in helper_store_hdecr() local
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H A Dmisc_helper.c50 CPUState *ccs; in helper_spr_core_write_generic() local
57 THREAD_SIBLING_FOREACH(cs, ccs) { in helper_spr_core_write_generic()
58 CPUPPCState *cenv = &POWERPC_CPU(ccs)->env; in helper_spr_core_write_generic()
67 CPUState *ccs; in helper_spr_write_CTRL() local
79 THREAD_SIBLING_FOREACH(cs, ccs) { in helper_spr_write_CTRL()
80 CPUPPCState *cenv = &POWERPC_CPU(ccs)->env; in helper_spr_write_CTRL()
201 CPUState *ccs; in helper_store_ptcr() local
203 THREAD_SIBLING_FOREACH(cs, ccs) { in helper_store_ptcr()
204 PowerPCCPU *ccpu = POWERPC_CPU(ccs); in helper_store_ptcr()
207 tlb_flush(ccs); in helper_store_ptcr()
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/openbmc/linux/Documentation/userspace-api/media/drivers/
H A Dccs.rst5 MIPI CCS camera sensor driver
8 The MIPI CCS camera sensor driver is a generic driver for `MIPI CCS
62 The MIPI CCS driver implements a number of private controls under
63 ``V4L2_CID_USER_BASE_CCS`` to control the MIPI CCS compliant camera sensors.
68 The CCS defines an analogue gain model where the gain can be calculated using
87 The CCS defines another analogue gain model called alternate analogue gain. In
100 The CCS standard supports lens shading correction. The feature can be controlled
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_migrate.c489 * DOC: Flat-CCS - Memory compression for Local memory
491 * On Xe-HP and later devices, we use dedicated compression control state (CCS)
495 * The memory required for the CCS of the entire local memory is 1/256 of the
497 * for the CCS data and a secure register will be programmed with the CCS base
500 * Flat CCS data needs to be cleared when a lmem object is allocated.
501 * And CCS data can be copied in and out of CCS region through
502 * XY_CTRL_SURF_COPY_BLT. CPU can't access the CCS data directly.
504 * I915 supports Flat-CCS on lmem only objects. When an objects has smem in
506 * content into smem. If the lmem object is Flat-CCS compressed by userspace,
508 * for such decompression. Hence I915 supports Flat-CCS only on lmem only objects.
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H A Dintel_gt_ccs_mode.c20 /* Build the value for the fixed CCS load balancing */ in intel_gt_apply_ccs_mode()
22 if (gt->ccs.cslices & BIT(cslice)) in intel_gt_apply_ccs_mode()
32 * unavailable if no CCS dispatches here in intel_gt_apply_ccs_mode()
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_fb.c20 * "The Color Control Surface (CCS) contains the compression status of
22 * is specified by 2 bits in the CCS. Each CCS cache-line represents
24 * cache-line-pairs. CCS is always Y tiled."
27 * each cache line in the CCS corresponds to an area of 32x16 cache
29 * us a ratio of one byte in the CCS for each 8x16 pixels in the
44 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
45 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
47 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
146 } ccs; member
164 .ccs.packed_aux_planes = BIT(1),
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/openbmc/u-boot/board/ti/ks2_evm/
H A DREADME70 Texas Instruments code composure studio (CCS) and for UART boot.
83 Load and Run U-Boot on keystone EVMs using CCS
86 Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin
87 on EVM. See instructions at below link for installing CCS on a Windows PC.
101 Start CCS on a Windows machine and Launch Target
137 1. Start CCS and run U-Boot as described above.
141 through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E/K2L
142 EVM using CCS", but using address 0x87000000.
158 1. Start CCS and run U-Boot as described above.
162 through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
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/openbmc/openbmc/poky/meta/recipes-extended/zip/zip-3.0/
H A D0001-configure-use-correct-CPP.patch30 -[ -f /usr/ccs/lib/cpp ] && CPP="/usr/ccs/lib/cpp -P"
36 +# [ -f /usr/ccs/lib/cpp ] && CPP="/usr/ccs/lib/cpp -P"
/openbmc/qemu/include/standard-headers/drm/
H A Ddrm_fourcc.h552 * Intel color control surface (CCS) for render compression
556 * the CCS will be plane index 1.
558 * Each CCS tile matches a 1024x512 pixel area of the main surface.
559 * To match certain aspects of the 3D hardware the CCS is
561 * the CCS pitch must be specified in multiples of 128 bytes.
563 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
572 * Intel color control surfaces (CCS) for Gen-12 render compression.
574 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
575 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
576 * main surface. In other words, 4 bits in CCS map to a main surface cache
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/openbmc/openbmc/meta-security/recipes-mac/ccs-tools/
H A Dccs-tools_1.8.9.bb2 …ecurity=tomoyo TOMOYO_trigger=/usr/lib/systemd/systemd \nTo initialize: \n/usr/lib/ccs/init_policy"
6 LIC_FILES_CHKSUM = "file://COPYING.ccs;md5=751419260aa954499f7abaabaa882bbe"
45 ${libdir}/ccs/.debug/* \
/openbmc/linux/include/uapi/drm/
H A Ddrm_fourcc.h551 * Intel color control surface (CCS) for render compression
555 * the CCS will be plane index 1.
557 * Each CCS tile matches a 1024x512 pixel area of the main surface.
558 * To match certain aspects of the 3D hardware the CCS is
560 * the CCS pitch must be specified in multiples of 128 bytes.
562 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
571 * Intel color control surfaces (CCS) for Gen-12 render compression.
573 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
574 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
575 * main surface. In other words, 4 bits in CCS map to a main surface cache
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/openbmc/qemu/backends/
H A Dcryptodev-vhost.c189 cc = b->conf.peers.ccs[i]; in cryptodev_vhost_start()
210 cc = b->conf.peers.ccs[i]; in cryptodev_vhost_start()
233 cc = b->conf.peers.ccs[i]; in cryptodev_vhost_start()
258 cc = b->conf.peers.ccs[i]; in cryptodev_vhost_stop()
282 cc = b->conf.peers.ccs[queue]; in cryptodev_vhost_virtqueue_mask()
298 cc = b->conf.peers.ccs[queue]; in cryptodev_vhost_virtqueue_pending()
H A Dcryptodev-vhost-user.c107 options.cc = b->conf.peers.ccs[i]; in cryptodev_vhost_user_start()
207 backend->conf.peers.ccs[i] = cc; in cryptodev_vhost_user_init()
241 backend->conf.peers.ccs[queue_index]; in cryptodev_vhost_user_crypto_create_session()
311 backend->conf.peers.ccs[queue_index]; in cryptodev_vhost_user_close_session()
347 cc = backend->conf.peers.ccs[i]; in cryptodev_vhost_user_cleanup()
350 backend->conf.peers.ccs[i] = NULL; in cryptodev_vhost_user_cleanup()

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