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Searched full:bwadj (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/arm/mach-keystone/
H A Dclock.c62 u32 pllm, plld, bwadj; in configure_mult_div() local
75 /* Program BWADJ */ in configure_mult_div()
76 bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */ in configure_mult_div()
79 (bwadj << CFG_PLLCTL0_BWADJ_SHIFT) & in configure_mult_div()
81 bwadj = bwadj >> CFG_PLLCTL0_BWADJ_BITS; in configure_mult_div()
83 CFG_PLLCTL1_BWADJ_MASK, bwadj); in configure_mult_div()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dbaikal,bt1-ccu-pll.yaml68 BWADJ--->
72 output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
/openbmc/linux/drivers/clk/
H A Dclk-k210.c312 u32 bwadj; member
410 reg |= FIELD_PREP(K210_PLL_BWADJ, pll_cfg->bwadj); in k210_pll_enable_hw()
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c108 * BWADJ should be set to NF / 2 to ensure the nominal bandwidth. in rkclk_set_pll()
/openbmc/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_csr.h1399 * BWADJ value