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/openbmc/u-boot/arch/arm/mach-keystone/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2012-2014
46 if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK)) in wait_for_completion()
53 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK | in bypass_main_pll()
62 u32 pllm, plld, bwadj; in configure_mult_div() local
64 pllm = data->pll_m - 1; in configure_mult_div()
65 plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK; in configure_mult_div()
68 if (data->pll == MAIN_PLL) in configure_mult_div()
69 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); in configure_mult_div()
71 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, in configure_mult_div()
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
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/openbmc/linux/drivers/clk/
H A Dclk-k210.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #define pr_fmt(fmt) "k210-clk: " fmt
15 #include <linux/clk-provider.h>
18 #include <soc/canaan/k210-sysctl.h>
20 #include <dt-bindings/clock/k210-clk.h>
312 u32 bwadj; member
322 * struct k210_sysclk - sysclk driver data
356 pll->id = pllid; in k210_init_pll()
357 pll->reg = regs + k210_plls_cfg[pllid].reg; in k210_init_pll()
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/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Andy Yan <andy.yan@rock-chips.com>
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
21 #include <dt-bindings/clock/rk3368-cru.h>
66 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
68 con = readl(&pll->con3); in rkclk_pll_get_rate()
74 con = readl(&pll->con0); in rkclk_pll_get_rate()
77 con = readl(&pll->con1); in rkclk_pll_get_rate()
91 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
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/openbmc/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_csr.h1 /* SPDX-License-Identifier: GPL-2.0 */
151 /* Mailbox PF->VF PF Accessible Data registers */
206 * struct ucd_core_eid_ucode_block_num - Core Eid to Ucode Blk Mapping Registers
226 * struct aqm_grp_execmsk_lo - Available AE engines for the group
243 * struct aqm_grp_execmsk_hi - Available AE engines for the group
260 * struct aqmq_drbl - AQM Queue Doorbell Counter Registers
277 * struct aqmq_qsz - AQM Queue Host Queue Size Registers
295 * struct aqmq_cmp_thr - AQM Queue Commands Completed Threshold Registers
313 * struct aqmq_cmp_cnt - AQM Queue Commands Completed Count Registers
337 * struct aqmq_en - AQM Queue Enable Registers
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