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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Drockchip-rga.yaml76 clocks = <&cru ACLK_RGA>,
/openbmc/u-boot/include/dt-bindings/clock/
H A Drk3188-cru-common.h64 #define ACLK_RGA 201 macro
H A Drv1108-cru.h101 #define ACLK_RGA 204 macro
H A Drk3368-cru.h98 #define ACLK_RGA 200 macro
H A Drk3328-cru.h124 #define ACLK_RGA 214 macro
H A Drk3288-cru.h94 #define ACLK_RGA 200 macro
H A Drk3399-cru.h166 #define ACLK_RGA 220 macro
/openbmc/linux/include/dt-bindings/clock/
H A Drk3188-cru-common.h64 #define ACLK_RGA 201 macro
H A Drk3228-cru.h85 #define ACLK_RGA 205 macro
H A Drk3128-cru.h84 #define ACLK_RGA 205 macro
H A Drv1108-cru.h98 #define ACLK_RGA 204 macro
H A Dpx30-cru.h108 #define ACLK_RGA 183 macro
H A Drk3368-cru.h95 #define ACLK_RGA 200 macro
H A Drk3328-cru.h125 #define ACLK_RGA 154 macro
H A Drk3288-cru.h99 #define ACLK_RGA 200 macro
H A Drockchip,rv1126-cru.h240 #define ACLK_RGA 174 macro
H A Drk3399-cru.h168 #define ACLK_RGA 220 macro
H A Drk3568-cru.h306 #define ACLK_RGA 243 macro
/openbmc/linux/Documentation/devicetree/bindings/power/
H A Drockchip,power-controller.yaml216 clocks = <&cru ACLK_RGA>,
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3128.c460 GATE(ACLK_RGA, "aclk_rga", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
H A Dclk-rk3228.c532 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
H A Dclk-rv1108.c453 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1_pre", 0,
H A Dclk-rk3188.c487 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk322x.dtsi206 <&cru ACLK_RGA>,
698 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
H A Drk3288.dtsi753 * ACLK_RGA is on ACLK_RGA_NIU.
772 <&cru ACLK_RGA>,
1012 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;

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