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/openbmc/linux/include/linux/mfd/
H A Dmotorola-cpcap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2007-2009 Motorola, Inc.
46 #define CPCAP_REG_ASSIGN6 0x0044 /* Resource Assignment 6 */
90 #define CPCAP_REG_S6C 0x062c /* Switcher 6 Control */
151 #define CPCAP_REG_ADCD6 0x0c20 /* A/D Converter Data 6 */
186 #define CPCAP_REG_OWDC 0x0eb0 /* One Wire Device Control */
199 #define CPCAP_REG_GPIO6 0x0ee4 /* GPIO 6 Control */
212 #define CPCAP_REG_OW1C 0x1200 /* One Wire 1 Command */
213 #define CPCAP_REG_OW1D 0x1204 /* One Wire 1 Data */
214 #define CPCAP_REG_OW1I 0x1208 /* One Wire 1 Interrupt */
[all …]
/openbmc/linux/include/linux/platform_data/
H A Dusb-omap1.h15 * - "A" connector (rectagular)
17 * - "B" connector (squarish) or "Mini-B"
19 * - "Mini-AB" connector (very similar to Mini-B)
24 u8 otg; /* port number, 1-based: usb1 == 2 */
35 * 2 == usb0-only, using internal transceiver
36 * 3 == 3 wire bidirectional
37 * 4 == 4 wire bidirectional
38 * 6 == 6 wire unidirectional (or TLL)
/openbmc/linux/Documentation/devicetree/bindings/input/touchscreen/
H A Dti,am3359-tsc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/touchscreen/ti,am3359-tsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
14 const: ti,am3359-tsc
17 description: Wires refer to application modes i.e. 4/5/8 wire touchscreen
22 ti,x-plate-resistance:
26 ti,coordinate-readouts:
34 maximum: 6
[all …]
/openbmc/linux/drivers/w1/masters/
H A Dsgi_w1.c1 // SPDX-License-Identifier: GPL-2.0
3 * sgi_w1.c - w1 master driver for one wire support in SGI ASICs
13 #include <linux/platform_data/sgi-w1.h>
41 * reset the device on the One Wire interface
49 writel(MCR_PACK(520, 65), dev->mcr); in sgi_w1_reset_bus()
50 ret = sgi_w1_wait(dev->mcr); in sgi_w1_reset_bus()
56 * this is the low level routine to read/write a bit on the One Wire
66 writel(MCR_PACK(6, 13), dev->mcr); in sgi_w1_touch_bit()
68 writel(MCR_PACK(80, 30), dev->mcr); in sgi_w1_touch_bit()
70 ret = sgi_w1_wait(dev->mcr); in sgi_w1_touch_bit()
[all …]
H A Dmxc_w1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
22 # define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
23 # define MXC_W1_CONTROL_PST BIT(6)
37 * reset the device on the One Wire interface
45 writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_reset_bus()
53 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_reset_bus()
55 /* PST bit is valid after the RPP bit is self-cleared */ in mxc_w1_ds2_reset_bus()
64 * this is the low level routine to read/write a bit on the One Wire
73 writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_touch_bit()
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dsama5d4.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Chip-specific header file for the SAMA5D4 SoC
21 #define ATMEL_ID_USART0 6 /* USART 0 */
31 #define ATMEL_ID_MATRIX1 17 /* H32MX, 32-bit AHB Matrix */
32 #define ATMEL_ID_MATRIX0 18 /* H64MX, 64-bit AHB Matrix */
35 #define ATMEL_ID_SMC 22 /* Multi-bit ECC interrupt */
45 #define ATMEL_ID_TWI0 32 /* Two-Wire Interface 0 */
46 #define ATMEL_ID_TWI1 33 /* Two-Wire Interface 1 */
47 #define ATMEL_ID_TWI2 34 /* Two-Wire Interface 2 */
55 #define ATMEL_ID_TC2 42 /* Timer Counter 2 (ch. 6, 7, 8) */
[all …]
H A Dat91sam9x5.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Chip-specific header file for the AT91SAM9x5 family
5 * Copyright (C) 2012-2013 Atmel Corporation.
24 #define ATMEL_ID_USART1 6 /* USART 1 */
27 #define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */
28 #define ATMEL_ID_TWI1 10 /* Two-Wire Interface 1 */
29 #define ATMEL_ID_TWI2 11 /* Two-Wire Interface 2 */
H A Dsama5d3.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Chip-specific header file for the SAMA5D3 family
5 * (C) 2012 - 2013 Atmel Corporation.
23 #define ATMEL_ID_SMC 5 /* Multi-bit ECC Interrupt */
24 #define ATMEL_ID_PIOA 6 /* Parallel I/O Controller A */
36 #define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */
37 #define ATMEL_ID_TWI1 19 /* Two-Wire Interface 1 */
38 #define ATMEL_ID_TWI2 20 /* Two-Wire Interface 2 */
106 /* Reserved: 0xf003c000 - 0xf8000000 */
124 /* Reserved: 0xf804400 - 0xffffc00 */
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/openbmc/openbmc/meta-raspberrypi/recipes-connectivity/bluez5/bluez5/
H A D0001-bcm43xx-Add-bcm43xx-3wire-variant.patch4 Subject: [PATCH] bcm43xx: Add bcm43xx-3wire variant
6 ---
7 Upstream-Status: Pending
12 diff --git a/tools/hciattach.c b/tools/hciattach.c
14 --- a/tools/hciattach.c
16 @@ -1078,6 +1078,9 @@ struct uart_t uart[] = {
20 + { "bcm43xx-3wire", 0x0000, 0x0000, HCI_UART_3WIRE, 115200, 3000000,
/openbmc/linux/fs/smb/server/
H A Dunicode.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * cifs_mapchar() - convert a host-endian char to proper char in codepage
19 * @from: host-endian source string
73 len = cp->uni2char(src_char, target, NLS_MAX_CHARSET_SIZE); in cifs_mapchar()
81 if (strcmp(cp->charset, "utf8")) in cifs_mapchar()
83 len = utf16s_to_utf8s(from, 3, UTF16_LITTLE_ENDIAN, target, 6); in cifs_mapchar()
95 * smb_utf16_bytes() - compute converted string length
137 * smb_from_utf16() - convert utf16le string to local charset
145 * Convert a little-endian utf16le string (as sent by the server) to a string
153 * Note that some windows versions actually send multiword UTF-16 characters
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dti,lmk04832.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Beguin <liambeguin@gmail.com>
21 - ti,lmk04832
26 '#address-cells':
29 '#size-cells':
32 '#clock-cells':
35 spi-max-frequency:
40 - description: PLL2 reference clock.
[all …]
/openbmc/linux/arch/sh/include/mach-common/mach/
H A Dhighlander.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define PA_SDPOW (-1)
62 #define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */
63 #define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */
64 #define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */
65 #define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
66 #define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
75 #define PA_POFF (-1)
114 #define PA_SMCR (PA_BCR+0x0500) /* 2-wire Serial control */
115 #define PA_SMSMADR (PA_BCR+0x0502) /* 2-wire Serial Slave control */
[all …]
/openbmc/u-boot/board/nokia/rx51/
H A Dtag_omap.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2011-2012
9 * (C) Copyright 2004-2005
16 * arch/arm/plat-omap/include/mach/board.h
18 * Information structures for board-specific data
65 * - "A" connector (rectagular)
67 * - "B" connector (squarish) or "Mini-B"
69 * - "Mini-AB" connector (very similar to Mini-B)
74 u8 otg; /* port number, 1-based: usb1 == 2 */
83 * 2 == usb0-only, using internal transceiver
[all …]
/openbmc/linux/Documentation/hwmon/
H A Dasc7621.rst20 Andigilog has both the PECI and pre-PECI versions of the Heceta-6, as
21 Intel calls them. Heceta-6e has high frequency PWM and Heceta-6p has
23 Heceta-6e part and aSC7621 is the Heceta-6p part. They are both in
28 have used registers below 20h for vendor-specific functions in addition
29 to those in the Intel-specified vendor range.
32 The fan speed control uses this finer value to produce a "step-less" fan
33 PWM output. These two bytes are "read-locked" to guarantee that once a
34 high or low byte is read, the other byte is locked-in until after the
37 sheet says 10-bits of resolution, although you may find the lower bits
47 We offer GPIO features on the former VID pins. These are open-drain
[all …]
/openbmc/linux/net/rxrpc/
H A Dprotocol.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 typedef __be32 rxrpc_seq_net_t; /* on-the-wire Rx message sequence number */
14 typedef __be32 rxrpc_serial_net_t; /* on-the-wire Rx message serial number */
18 * on-the-wire Rx packet header
19 * - all multibyte fields should be in network byte order
23 #define RXRPC_RANDOM_EPOCH 0x80000000 /* Random if set, date-based if not */
27 #define RXRPC_CHANNELMASK (RXRPC_MAXCALLS-1) /* mask for channel ID */
32 __be32 callNumber; /* call ID (0 for connection-level packets) */
42 #define RXRPC_PACKET_TYPE_CHALLENGE 6 /* connection security challenge (SRVR->CLNT) */
43 #define RXRPC_PACKET_TYPE_RESPONSE 7 /* connection secutity response (CLNT->SRVR) */
[all …]
H A Doutput.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "ar-internal.h"
23 struct sockaddr *sa = msg->msg_name; in do_udp_sendmsg()
24 struct sock *sk = socket->sk; in do_udp_sendmsg()
27 if (sa->sa_family == AF_INET6) { in do_udp_sendmsg()
28 if (sk->sk_family != AF_INET6) { in do_udp_sendmsg()
30 return -ENOPROTOOPT; in do_udp_sendmsg()
51 u16 tx_backoff = READ_ONCE(call->tx_backoff); in rxrpc_tx_backoff()
54 WRITE_ONCE(call->tx_backoff, tx_backoff + 1); in rxrpc_tx_backoff()
56 WRITE_ONCE(call->tx_backoff, 0); in rxrpc_tx_backoff()
[all …]
/openbmc/linux/drivers/infiniband/core/
H A Dud_header.c15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
216 .offset_words = 6,
289 iph.tos = header->ip4.tos; in ib_ud_ip4_csum()
290 iph.tot_len = header->ip4.tot_len; in ib_ud_ip4_csum()
291 iph.id = header->ip4.id; in ib_ud_ip4_csum()
292 iph.frag_off = header->ip4.frag_off; in ib_ud_ip4_csum()
293 iph.ttl = header->ip4.ttl; in ib_ud_ip4_csum()
294 iph.protocol = header->ip4.protocol; in ib_ud_ip4_csum()
296 iph.saddr = header->ip4.saddr; in ib_ud_ip4_csum()
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/openbmc/linux/Documentation/i2c/
H A Dsummary.rst6 a protocol developed by Philips. It is a slow two-wire protocol (variable
12 e.g. TWI (Two Wire Interface), IIC.
14 The latest official I2C specification is the `"I2C-bus specification and user
16 published by NXP Semiconductors. However, you need to log-in to the site to
17 access the PDF. An older version of the specification (revision 6) is archived
18 `here <https://web.archive.org/web/20210813122132/https://www.nxp.com/docs/en/user-guide/UM10204.pd…
39 .. kernel-figure:: i2c_bus.svg
57 video-related chips.
/openbmc/linux/sound/ppc/
H A Dsnd_ps3_reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
39 * three wire serial
73 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
75 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
81 #define PS3_AUDIO_INTR_0_CHAN6 PS3_AUDIO_INTR_0_CHAN(6)
96 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
98 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
106 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
108 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
125 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
[all …]
/openbmc/openbmc/meta-raspberrypi/docs/
H A Dextra-build-config.md6 <http://www.yoctoproject.org/docs/latest/ref-manual/ref-manual.html>
32 See: <https://www.raspberrypi.com/documentation/computers/config_txt.html#memory-options>
36 …erland`. Be aware that `userland` has not support for 64-bit arch. If you disable `vc4` on a 64-bi…
50 See: <https://www.raspberrypi.com/documentation/computers/config_txt.html#licence-key-and-codec-opt…
85 …b`. The "mmc" is required to load an image from the SD card, following the u-boot specification. S…
106 OVER_VOLTAGE = "6"
108 See: <https://www.raspberrypi.com/documentation/computers/config_txt.html#overclocking-options>
125 See: <https://www.raspberrypi.com/documentation/computers/configuration.html#hdmi-configuration>
140 This will enable the firmware to fall back to off-line compositing of Dispmanx
141 elements. Normally the compositing is done on-line, during scanout, but cannot
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/addac/
H A Dadi,ad74115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74115H is a single-channel software configurable input/output
17 chip solution with an SPI interface. The device features a 16-bit ADC and a
18 14-bit DAC.
25 - adi,ad74115h
30 spi-max-frequency:
33 spi-cpol: true
[all …]
/openbmc/linux/drivers/iommu/
H A Dirq_remapping.c1 // SPDX-License-Identifier: GPL-2.0-only
33 * With interrupt-remapping, for now we will use virtual wire A in irq_remapping_restore_boot_irq_mode()
34 * mode, as virtual wire B is little complex (need to configure in irq_remapping_restore_boot_irq_mode()
35 * both IOAPIC RTE as well as interrupt-remapping table entry). in irq_remapping_restore_boot_irq_mode()
58 return -EINVAL; in setup_irqremap()
71 else if (!strncmp(str, "nopost", 6)) in setup_irqremap()
93 return (remap_ops->capability & (1 << cap)); in irq_remapping_cap()
100 return -ENOSYS; in irq_remapping_prepare()
112 return -ENOSYS; in irq_remapping_prepare()
121 if (!remap_ops->enable) in irq_remapping_enable()
[all …]
/openbmc/u-boot/cmd/
H A Dw1.c1 /* SPDX-License-Identifier: GPL-2.0+
10 #include <w1-eeprom.h>
11 #include <dm/device-internal.h>
20 printf("one wire interface not found\n"); in w1_bus()
23 printf("Bus %d:\t%s", bus->seq, bus->name); in w1_bus()
33 printf("\t%s (%d) uclass %s : ", dev->name, dev->seq, in w1_bus()
34 dev->uclass->uc_drv->name); in w1_bus()
71 printf("one wire interface not found\n"); in w1_read()
88 if (strcmp(dev->uclass->uc_drv->name, "w1_eeprom")) { in w1_read()
95 printf("error reading device %s\n", dev->name); in w1_read()
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/openbmc/qemu/tests/unit/
H A Dtest-vmstate.c28 #include "migration/qemu-file-types.h"
29 #include "../migration/qemu-file.h"
32 #include "io/channel-file.h"
85 static void compare_vmstate(const uint8_t *wire, size_t size) in compare_vmstate() argument
97 SUCCESS(memcmp(result, wire, size)); in compare_vmstate()
101 g_assert_cmpint(qemu_file_get_error(f), ==, -EIO); in compare_vmstate()
107 int version, const uint8_t *wire, size_t size) in load_vmstate_one() argument
113 qemu_put_buffer(f, wire, size); in load_vmstate_one()
131 int version, const uint8_t *wire, size_t size) in load_vmstate() argument
135 FAILURE(load_vmstate_one(desc, obj, version, wire, 0)); in load_vmstate()
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/openbmc/u-boot/drivers/w1/
H A Dmxc_w1.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for one wire controller in some i.MX Socs
8 * Newer i.MX SoCs such as the i.MX6 do not have one wire controllers.
29 #define MXC_W1_CONTROL_PST BIT(6)
30 #define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
53 * this is the low level routine to read/write a bit on the One Wire
59 u16 *ctrl_addr = &pdata->regs->control; in mxc_w1_touch_bit()
67 while (timeout_cnt--) { in mxc_w1_touch_bit()
80 struct mxc_w1_regs *regs = pdata->regs; in mxc_w1_read_byte()
93 readw(&regs->tx_rx); in mxc_w1_read_byte()
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