Searched +full:5 +full:g +full:- +full:usxgmii (Results 1 – 14 of 14) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Steen Hegelund <steen.hegelund@microchip.com>21 * Rx built-in fault detector (loss-of-lock/loss-of-signal)22 * Adjustable tx de-emphasis (FFE)31 The SERDES6G is a high-speed SERDES interface, which can operate at34 * 100 Mbps (100BASE-FX)35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)[all …]
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */4 * Copyright 2006-2009 Solarflare Communications Inc.23 #define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */36 #define MDIO_DEVS1 5 /* Devices in package */38 #define MDIO_CTRL2 7 /* 10G control 2 */39 #define MDIO_STAT2 8 /* 10G status 2 */40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */[all …]
2 --------3 The LX2160A Reference Design (RDB) is a high-performance computing,8 --------------------------------------9 For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc12 ----------------------14 Two ports of 72-bits (8-bits ECC) DDR4.15 Each port supports four chip-selects and two DIMM20 Serdes1: Supports two USXGMII connectors, each connected through32 eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC36 for off-board emulation[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright 2018-2019 NXP19 #include <fsl-mc/fsl_mc.h>20 #include <fsl-mc/ldpaa_wriop.h>57 /* -1 terminated array */66 * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII67 * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)69 * to any of the 8 IO slots (IO slot 1 - IO slot 8)).70 * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card78 {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},[all …]
7 5. LS1046A13 ---------14 The LS1043A integrated multicore processor combines four ARM Cortex-A5320 - Four 64-bit ARM Cortex-A53 CPUs21 - 1 MB unified L2 Cache22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the26 - Packet parsing, classification, and distribution (FMan)27 - Queue management for scheduling, packet sequencing, and congestion29 - Hardware buffer management for buffer allocation and de-allocation (BMan)[all …]
1 // SPDX-License-Identifier: GPL-2.056 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5149 /* Sleep and timeout for checking if the Processor-Intensive197 int len_l = min(stat->size, 16); in aqr107_get_stat()198 int len_h = stat->size - len_l; in aqr107_get_stat()202 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); in aqr107_get_stat()206 ret = val & GENMASK(len_l - 1, 0); in aqr107_get_stat()208 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); in aqr107_get_stat()212 ret += (val & GENMASK(len_h - 1, 0)) << 16; in aqr107_get_stat()221 struct aqr107_priv *priv = phydev->priv; in aqr107_get_stats()[all …]
1 // SPDX-License-Identifier: GPL-2.04 * technologies such as SFP cages where the PHY is hot-pluggable.44 * struct phylink - internal data type for phylink60 u8 link_port; /* The current non-phy ethtool port */93 if ((pl)->config->type == PHYLINK_NETDEV) \94 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \95 else if ((pl)->config->type == PHYLINK_DEV) \96 dev_printk(level, (pl)->dev, fmt, ##__VA_ARGS__); \108 if ((pl)->config->type == PHYLINK_NETDEV) \109 netdev_dbg((pl)->netdev, fmt, ##__VA_ARGS__); \[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Marvell 10G 88x3310 PHY driver10 * via observation and experimentation for a setup using single-lane Serdes:12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber18 * XAUI PHYXS -- <appropriate PCS as above>104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */[all …]
1 // SPDX-License-Identifier: GPL-2.0+52 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */53 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */54 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */113 * it can safely re-enter loopback mode. Record the time when133 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) +134 * 3.0762e-1*(N^1) + -5.2156e1136 * where [-52.156, 137.961]C and N = [0, 1023].145 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) +146 * 307620e-3*(N^1) + -52156[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later35 err = mdiodev_c45_read(&mpcs->mdio, MDIO_MMD_PHYXS, regnum); in mv88e639x_read()46 return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, val); in mv88e639x_write()52 return mdiodev_c45_modify(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, mask, in mv88e639x_modify()59 return mdiodev_c45_modify_changed(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, in mv88e639x_modify_changed()73 mpcs->mdio.dev.parent = dev; in mv88e639x_pcs_alloc()74 mpcs->mdio.bus = bus; in mv88e639x_pcs_alloc()75 mpcs->mdio.addr = addr; in mv88e639x_pcs_alloc()77 snprintf(mpcs->name, sizeof(mpcs->name), in mv88e639x_pcs_alloc()78 "mv88e6xxx-%s-serdes-%d", dev_name(dev), port); in mv88e639x_pcs_alloc()[all …]
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1 // SPDX-License-Identifier: GPL-2.0-only9 #include <dt-bindings/phy/phy.h>10 #include <dt-bindings/phy/phy-cadence.h>12 #include <linux/clk-provider.h>239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",279 [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),325 #define LINK1_MASK GENMASK(5, 3)464 for (i = 0; i < tbl->num_entries; i++) { in cdns_torrent_get_tbl_vals()[all …]
1 // SPDX-License-Identifier: GPL-2.010 #include <linux/pcs/pcs-xpcs.h>14 #include "pcs-xpcs.h"167 const struct xpcs_compat *compat = &id->compat[i]; in xpcs_find_compat()169 for (j = 0; j < compat->num_interfaces; j++) in xpcs_find_compat()170 if (compat->interface[j] == interface) in xpcs_find_compat()181 compat = xpcs_find_compat(xpcs->id, interface); in xpcs_get_an_mode()183 return -ENODEV; in xpcs_get_an_mode()185 return compat->an_mode; in xpcs_get_an_mode()194 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) in __xpcs_linkmode_supported()[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c79 * Set phydev->irq to PHY_POLL if interrupts are not supported,83 #define PHY_POLL -184 #define PHY_MAC_INTERRUPT -293 * enum phy_interface_t - Interface Mode definitions95 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch97 * @PHY_INTERFACE_MODE_MII: Media-independent interface98 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface99 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface[all …]