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/openbmc/linux/Documentation/fb/
H A Dviafb.modes15 # Sync Width 3.813 us 0.064 ms
17 # Front Porch 0.636 us 0.318 ms
19 # Back Porch 1.907 us 1.048 ms
21 # Active Time 25.422 us 15.253 ms
23 # Blank Time 6.356 us 1.430 ms
40 # Sync Width 2.032 us 0.080 ms
42 # Front Porch 0.508 us 0.027 ms
44 # Back Porch 3.810 us 0.427 ms
46 # Active Time 20.317 us 12.800 ms
48 # Blank Time 6.349 us 0.533 ms
[all …]
/openbmc/linux/drivers/usb/storage/
H A Dkarma.c30 #define RIO_SEND_LEN 40
42 static int rio_karma_init(struct us_data *us);
87 * For each command we send 40 bytes starting 'RIOP\0' followed by
94 static int rio_karma_send_command(char cmd, struct us_data *us) in rio_karma_send_command() argument
99 struct karma_data *data = (struct karma_data *) us->extra; in rio_karma_send_command()
101 usb_stor_dbg(us, "sending command %04x\n", cmd); in rio_karma_send_command()
102 memset(us->iobuf, 0, RIO_SEND_LEN); in rio_karma_send_command()
103 memcpy(us->iobuf, RIO_PREFIX, RIO_PREFIX_LEN); in rio_karma_send_command()
104 us->iobuf[5] = cmd; in rio_karma_send_command()
105 us->iobuf[6] = seq; in rio_karma_send_command()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml36 richtek,ld-pulse-delay-us:
43 richtek,ld-pulse-width-us:
50 richtek,fsin1-delay-us:
57 richtek,fsin1-width-us:
60 minimum: 40
64 richtek,fsin2-delay-us:
71 richtek,fsin2-width-us:
74 minimum: 40
78 richtek,es-pulse-width-us:
H A Drichtek,rt6245-regulator.yaml55 delay time 0us, 10us, 20us, 40us. If this property is missing then keep
/openbmc/linux/Documentation/tools/rtla/
H A Drtla-osnoise-hist.rst37 histogram is set to group outputs in buckets of *10us* and *25* entries::
41 # Time unit is microseconds (us)
48 …40 0 0 0 0 0 4 2 7 2 …
54 …max: 30 30 20 20 30 40 40 40 40 …
H A Drtla-timerlat-top.rst35 **--aa-only** *us*
46 automatic trace mode, instructing the tracer to stop if a *40 us* latency or
49 # timerlat -a 40 -c 1-23 -q
51 0 00:00:12 | IRQ Timer Latency (us) | Thread Timer Latency (us)
78 IRQ handler delay: 27.49 us (65.52 %)
79 IRQ latency: 28.13 us
80 Timerlat IRQ duration: 9.59 us (22.85 %)
81 Blocking thread: 3.79 us (9.03 %)
82 objtool:49256 3.79 us
104 Thread latency: 41.96 us (100%)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dmax77620.txt91 -maxim,shutdown-fps-time-period-us: u32, FPS time period in microseconds
95 -maxim,suspend-fps-time-period-us: u32, FPS time period in microseconds
112 MAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds.
113 MAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
114 MAX77663 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
148 maxim,shutdown-fps-time-period-us = <1280>;
153 maxim,shutdown-fps-time-period-us = <1280>;
158 maxim,shutdown-fps-time-period-us = <1280>;
/openbmc/linux/Documentation/devicetree/bindings/power/
H A Ddomain-idle-state.yaml31 entry-latency-us:
34 state. Note that, the exit-latency-us duration may be guaranteed only
35 after the entry-latency-us has passed.
37 exit-latency-us:
42 min-residency-us:
59 - entry-latency-us
60 - exit-latency-us
61 - min-residency-us
71 entry-latency-us = <20>;
72 exit-latency-us = <40>;
[all …]
/openbmc/u-boot/board/barco/platinum/
H A Dspl_picon.c27 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
38 /* SDODT[0:1]: 100k pull-up, 40 ohm */
41 /* SDQS[0:7]: Differential input, 40 ohm */
50 /* DQM[0:7]: Differential input, 40 ohm */
68 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
70 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
72 /* DATA[00:63]: Differential input, 40 ohm */
135 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ in spl_dram_init()
136 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ in spl_dram_init()
H A Dspl_titanium.c27 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
38 /* SDODT[0:1]: 100k pull-up, 40 ohm */
41 /* SDQS[0:7]: Differential input, 40 ohm */
50 /* DQM[0:7]: Differential input, 40 ohm */
68 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
70 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
72 /* DATA[00:63]: Differential input, 40 ohm */
138 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ in spl_dram_init()
139 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ in spl_dram_init()
/openbmc/u-boot/board/freescale/mx6memcal/
H A Dspl.c58 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
69 /* SDODT[0:1]: 100k pull-up, 40 ohm */
72 /* SDQS[0:7]: Differential input, 40 ohm */
82 /* DQM[0:7]: Differential input, 40 ohm */
100 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
102 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
104 /* DATA[00:63]: Differential input, 40 ohm */
117 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
128 /* SDODT[0:1]: 100k pull-up, 40 ohm */
131 /* SDQS[0:7]: Differential input, 40 ohm */
[all …]
/openbmc/linux/drivers/regulator/
H A Drtmv20-regulator.c208 { "richtek,ld-pulse-delay-us", 0, 0, 100000, 100, RTMV20_REG_PULSEDELAY, in rtmv20_properties_init()
210 { "richtek,ld-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_PULSEWIDTH, in rtmv20_properties_init()
212 { "richtek,fsin1-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN1CTRL1, in rtmv20_properties_init()
214 { "richtek,fsin1-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN1CTRL3, in rtmv20_properties_init()
216 { "richtek,fsin2-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN2CTRL1, in rtmv20_properties_init()
218 { "richtek,fsin2-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN2CTRL3, in rtmv20_properties_init()
220 { "richtek,es-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_ESPULSEWIDTH, in rtmv20_properties_init()
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_rc6.c88 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we in gen11_rc6_enable()
90 * it takes us to service a CS interrupt and submit a new ELSP - that in gen11_rc6_enable()
99 * service latency, and puts it under 10us for Icelake, similar to in gen11_rc6_enable()
178 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we in gen9_rc6_enable()
180 * it takes us to service a CS interrupt and submit a new ELSP - that in gen9_rc6_enable()
189 * service latency, and puts it around 10us for Broadwell (and other in gen9_rc6_enable()
190 * big core) and around 40us for Broxton (and other low power cores). in gen9_rc6_enable()
191 * [Note that for legacy ringbuffer submission, this is less than 1us!] in gen9_rc6_enable()
192 * However, the wakeup latency on Broxton is closer to 100us. To be in gen9_rc6_enable()
223 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); in gen8_rc6_enable()
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dmac.h36 * @MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
442 * (0=SISO, 1=MIMO2) x (0-20MHz, 1-40MHz, 2-80MHz, 3-160MHz)
443 * Each entry contains 2 QAM thresholds for 8us and 16us:
446 * QAM_tx < QAM_th1 --> PPE=0us
447 * QAM_th1 <= QAM_tx < QAM_th2 --> PPE=8us
448 * QAM_th2 <= QAM_tx --> PPE=16us
452 * For rates between low_th and high_th, need 8us PPE
453 * For rates equal or higher then the high_th, need 16us PPE
454 * Nss (0-siso, 1-mimo2) x BW (0-20MHz, 1-40MHz, 2-80MHz, 3-160MHz) x
466 * (0=SISO, 1=MIMO2) x (0-20MHz, 1-40MHz, 2-80MHz, 3-160MHz)
[all …]
H A Drs.h38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
121 * @IWL_TLC_MCS_PER_BW_80: mcs for bw - 20Hhz, 40Hhz, 80Hhz
408 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
441 * 0 1xLTF+0.8us
442 * 1 2xLTF+0.8us
443 * 2 2xLTF+1.6us
444 * 3 & SGI (bit 13) clear 4xLTF+3.2us
445 * 3 & SGI (bit 13) set 4xLTF+0.8us
447 * 0 4xLTF+0.8us
448 * 1 2xLTF+0.8us
[all …]
/openbmc/linux/drivers/media/rc/img-ir/
H A Dimg-ir-jvc.c57 .unit = 527500, /* 527.5 us */
66 .pulse = { 1 /* 527.5 us +-60 us */ },
67 .space = { 1 /* 527.5 us */ },
71 .pulse = { 1 /* 527.5 us +-60 us */ },
72 .space = { 3 /* 1.5825 ms +-40 us */ },
/openbmc/linux/drivers/media/rc/
H A Dir-sharp-decoder.c15 #define SHARP_UNIT 40 /* us */
16 #define SHARP_BIT_PULSE (8 * SHARP_UNIT) /* 320us */
17 #define SHARP_BIT_0_PERIOD (25 * SHARP_UNIT) /* 1ms (680us space) */
18 #define SHARP_BIT_1_PERIOD (50 * SHARP_UNIT) /* 2ms (1680us space) */
19 #define SHARP_BIT_0_SPACE (17 * SHARP_UNIT) /* 680us space */
20 #define SHARP_BIT_1_SPACE (42 * SHARP_UNIT) /* 1680us space */
21 #define SHARP_ECHO_SPACE (1000 * SHARP_UNIT) /* 40 ms */
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dda7218.txt56 - dlg,jack-rate-us : Time between jack detect measurements (us)
57 [<5>, <10>, <20>, <40>, <80>, <160>, <320>, <640>]
97 dlg,jack-rate-us = <40>;
/openbmc/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml332 entry-latency-us:
336 exit-latency-us:
339 The exit-latency-us duration may be guaranteed only after
340 entry-latency-us has passed.
342 min-residency-us:
348 wakeup-latency-us:
354 entry-latency-us + exit-latency-us
358 systems entry-latency-us + exit-latency-us will exceed
359 wakeup-latency-us by this duration.
370 - entry-latency-us
[all …]
/openbmc/linux/Documentation/crypto/
H A Ddescore-readme.rst62 - 30us per encryption (options: 64k tables, no IP/FP)
63 - 33us per encryption (options: 64k tables, FIPS standard bit ordering)
64 - 45us per encryption (options: 2k tables, no IP/FP)
65 - 48us per encryption (options: 2k tables, FIPS standard bit ordering)
66 - 275us to set a new key (uses 1k of key tables)
80 - 53us per encryption (uses 2k of tables)
81 - 96us to set a new key (uses 2.25k of key tables)
86 more specifically, 19-40% slower on the 68020 and 11-35% slower
93 gcc 2.1 -O2 Sun 3/110 304 uS 369.5uS 461.8uS 22%
94 cc -O1 Sun 3/110 336 uS 436.6uS 399.3uS 19%
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dexynos5420-peach-pit.dts54 samsung,efuse-min-value = <40>;
114 * measure for fine tune b00: 1us,
115 * 01: 0.5us, 10:2us, 11:4us.
127 * NOF=40LSB for HBR CDR setting
131 0x04 0x7a 0xfd /* [7:5] DCO_FTRNG=+-40% */
294 samsung,vl-hbpd = <40>;
295 samsung,vl-hfpd = <40>;
/openbmc/linux/drivers/iio/humidity/
H A Ddht11.c34 #define DHT11_BITS_PER_READ 40
45 * 0-bit: 22-30uS -- typically 26uS (AM2302)
46 * 1-bit: 68-75uS -- typically 70uS (AM2302)
51 * timeres > 34uS ... don't know what a 1-tick pulse is
52 * 34uS > timeres > 30uS ... no problem (30kHz and 32kHz clocks)
53 * 30uS > timeres > 23uS ... don't know what a 2-tick pulse is
54 * timeres < 23uS ... no problem
59 * 40kHz, where this driver is most unreliable, there are two options.
63 #define DHT11_START_TRANSMISSION_MIN 18000 /* us */
64 #define DHT11_START_TRANSMISSION_MAX 20000 /* us */
/openbmc/openbmc/meta-phosphor/recipes-core/systemd/
H A Dsystemd_%.bbappend29 file://40-hardware-watchdog.conf \
33 ${systemd_unitdir}/system.conf.d/40-hardware-watchdog.conf \
38 install -m 0644 ${UNPACKDIR}/40-hardware-watchdog.conf ${D}${systemd_unitdir}/system.conf.d/
54 # 'shadow' which prevents us from putting it into the initramfs. We
/openbmc/openbmc-test-automation/docs/
H A Dcertificate_generate.md37 Country Name (2 letter code) [AU]:US
74 "Country": "US",
159 "Country": "US",
169 "Country": "US",
173 "ValidNotAfter": "2021-01-23T21:13:40+00:00",
174 "ValidNotBefore": "2019-09-11T21:13:40+00:00"
/openbmc/linux/drivers/input/joystick/
H A Dgf2k.c24 #define GF2K_START 400 /* The time we wait for the first bit [400 us] */
25 #define GF2K_STROBE 40 /* The time we wait for the first bit [40 us] */
42 static char gf2k_length[] = { 40, 40, 40, 40, 40, 40, 40, 40 };
166 t = GB(40,4,0); in gf2k_read()

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