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/openbmc/linux/drivers/cpufreq/
H A Dtegra194-cpufreq.c23 #define REF_CLK_MHZ 408 /* 408 MHz */
153 * [63:32] PLLP counter: Counts at fixed frequency (408 MHz)
213 * [31:0] PLLP counter: Counts at fixed frequency (408 MHz)
253 * pll_p(408MHz). in tegra_read_counters()
254 * It will take = 2 ^ 32 / 408 MHz to overflow ref clk counter in tegra_read_counters()
282 * = delta ref_clk_counter / (408 * 10^6) sec
285 * = (delta cycles * 408 * 10^6) / delta ref_clk_counter
286 * in KHz = (delta cycles * 408 * 10^3) / delta ref_clk_counter
/openbmc/openbmc/poky/meta/recipes-devtools/libtool/libtool/
H A D0003-libtool-remove-help2man-dependency.patch18 @@ -408,23 +408,6 @@ $(notes_txt): $(notes_texi)
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/fluentbit/fluentbit/
H A D0004-wasm-avoid-cmake-try_run-when-cross-compiling.patch34 @@ -408,7 +408,7 @@ if (WAMR_BUILD_STATIC_PGO EQUAL 1)
/openbmc/u-boot/board/sunxi/
H A Ddram_timings_sun4i.h22 # elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */
122 # elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066G @408MHz, timings: 8-7-7-16 */
/openbmc/linux/arch/mips/boot/dts/brcm/
H A Dbcm7358.dtsi100 upg_aon_irq0_intc: interrupt-controller@408b80 {
249 upg_gio_aon: gpio@408c00 {
359 mspi: spi@408a00 {
373 waketimer: waketimer@408e80 {
H A Dbcm7362.dtsi106 upg_aon_irq0_intc: interrupt-controller@408b80 {
248 upg_gio_aon: gpio@408c00 {
406 mspi: spi@408a00 {
420 waketimer: waketimer@408e80 {
H A Dbcm7360.dtsi100 upg_aon_irq0_intc: interrupt-controller@408b80 {
252 upg_gio_aon: gpio@408c00 {
410 mspi: spi@408a00 {
424 waketimer: waketimer@408e80 {
H A Dbcm7346.dtsi106 upg_aon_irq0_intc: interrupt-controller@408b80 {
276 upg_gio_aon: gpio@408c00 {
491 mspi: spi@408a00 {
505 waketimer: waketimer@408e80 {
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-core/sdbus-c++/sdbus-c++-libsystemd/
H A D0010-distinguish-XSI-compliant-strerror_r-from-GNU-specif.patch30 @@ -408,7 +408,12 @@ static void bus_error_strerror(sd_bus_error *e, int error) {
/openbmc/linux/Documentation/scsi/
H A DFlashPoint.rst142 be reached by electronic mail at techsup@buslogic.com, by Voice at +1 408
143 654-0760, or by FAX at +1 408 492-1542.
172 Contact BusLogic Technical Support at techsup@buslogic.com or +1 408
/openbmc/u-boot/configs/
H A Dbananapi_m2_zero_defconfig5 CONFIG_DRAM_CLK=408
H A Demlid_neutis_n5_devboard_defconfig5 CONFIG_DRAM_CLK=408
H A Dnanopi_m1_defconfig5 CONFIG_DRAM_CLK=408
H A Dnanopi_neo_plus2_defconfig5 CONFIG_DRAM_CLK=408
H A Dnanopi_m1_plus_defconfig5 CONFIG_DRAM_CLK=408
H A Dnanopi_neo_defconfig5 CONFIG_DRAM_CLK=408
H A DAuxtek-T003_defconfig5 CONFIG_DRAM_CLK=408
H A Dnanopi_neo_air_defconfig5 CONFIG_DRAM_CLK=408
H A DA13-OLinuXinoM_defconfig5 CONFIG_DRAM_CLK=408
H A DLinksprite_pcDuino3_Nano_defconfig5 CONFIG_DRAM_CLK=408
H A DA13-OLinuXino_defconfig5 CONFIG_DRAM_CLK=408
H A Dinet97fv2_defconfig5 CONFIG_DRAM_CLK=408
H A Dinet9f_rev03_defconfig5 CONFIG_DRAM_CLK=408
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dcpu.c43 * to 408 to satisfy the requirement of having at least 16 CPU clock in enable_cpu_power_rail()
48 setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408); in enable_cpu_power_rail()
155 * PLLP base of 408MHz. in t114_init_clocks()
/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dplatform.S68 * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
339 /* ldr r2, =0x019001F0 @ load PLL parameter for 24Mhz CLKIN (408:336) */
533 ldr r1, =0x000000FA @ 408 MHz
564 ldr r1, =0x00000089 @ 408 MHz
571 ldr r1, =0x000000E2 @ 408 MHz
627 ldr r1, =0x33302825 @ 408 MHz
648 ldr r1, =0xCC00963F @ 408 MHz
660 ldr r1, =0x00002323 @ 408 MHz
716 ldr r1, =0x04001700 @ 408 MHz
724 ldr r1, =0x00000000 @ 408 MHz
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