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/openbmc/linux/include/soc/mscc/
H A Docelot_dev.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
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/openbmc/linux/include/linux/mfd/abx500/
H A Dab8500-sysctrl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) ST-Ericsson SA 2010
83 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
84 #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
85 #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
86 #define AB8500_TURNONSTATUS_RTCALARM BIT(3)
87 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
88 #define AB8500_TURNONSTATUS_VBUSDET BIT(5)
89 #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
91 #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
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/openbmc/u-boot/drivers/sound/
H A Dmax98090.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * max98090.h -- MAX98090 ALSA SoC Audio driver
66 /* MAX98090 Registers Bit Fields */
71 #define M98090_SWRESET_MASK BIT(7)
76 #define M98090_SR_96K_MASK BIT(5)
79 #define M98090_SR_32K_MASK BIT(4)
80 #define M98090_SR_32K_SHIFT 4
82 #define M98090_SR_48K_MASK BIT(3)
85 #define M98090_SR_44K1_MASK BIT(2)
88 #define M98090_SR_16K_MASK BIT(1)
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/openbmc/linux/include/linux/mfd/da9062/
H A Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2015-2017 Dialog Semiconductor
151 * Bit fields
158 #define DA9062AA_WRITE_MODE_MASK BIT(6)
160 #define DA9062AA_REVERT_MASK BIT(7)
166 #define DA9062AA_DVC_BUSY_MASK BIT(2)
172 #define DA9062AA_GPI1_MASK BIT(1)
174 #define DA9062AA_GPI2_MASK BIT(2)
176 #define DA9062AA_GPI3_MASK BIT(3)
177 #define DA9062AA_GPI4_SHIFT 4
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/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_128M16_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
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H A Dkwbimage_256M8_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
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/openbmc/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddpkg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2015 Freescale Semiconductor Inc.
16 * DPKG_NUM_OF_MASKS - Number of masks per key extraction
18 #define DPKG_NUM_OF_MASKS 4
21 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
26 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
38 * enum dpkg_extract_type - Enumeration for selecting extraction type
41 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
52 * struct dpkg_mask - A structure for defining a single extraction mask
64 #define NH_FLD_ETH_DA BIT(0)
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/openbmc/linux/include/linux/mfd/
H A Dtps65219.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
89 #define TPS65219_REG_INT_SYS_POS 4
103 #define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6)
104 #define TPS65219_BUCKS_BW_SEL_MASK BIT(7)
106 #define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT)
107 #define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7)
109 #define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0)
110 #define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1)
111 #define TPS65219_ENABLE_BUCK3_EN_MASK BIT(2)
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H A Drohm-bd71815.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 * Author: yanglsh@embest-tech.com
32 /* LDO for Low-Power State Retention */
236 #define BD71815_BUCK_PWM_FIXED BIT(4)
237 #define BD71815_BUCK_SNVS_ON BIT(3)
238 #define BD71815_BUCK_RUN_ON BIT(2)
239 #define BD71815_BUCK_LPSR_ON BIT(1)
240 #define BD71815_BUCK_SUSP_ON BIT(0)
243 #define BD71815_BUCK_DVSSEL BIT(7)
244 #define BD71815_BUCK_STBY_DVS BIT(6)
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H A Dlp87565.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
97 #define LP87565_BUCK_CTRL_1_EN BIT(7)
98 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6)
101 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3)
102 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2)
103 #define LP87565_BUCK_CTRL_1_FPWM BIT(1)
105 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0)
119 #define LP87565_RESET_SW_RESET BIT(0)
121 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7)
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/openbmc/linux/drivers/staging/vme_user/
H A Dvme_tsi148.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 #define TSI148_MAX_MAILBOX 4 /* Max Mail Box registers */
37 void (*lm_callback[4])(void *); /* Called in interrupt handler */
38 void *lm_data[4];
50 * Layout of a DMAC Linked-List Descriptor
53 * correctly laid out - It must also be aligned on 64-bit boundaries.
70 * The descriptor needs to be aligned on a 64-bit boundary, we increase
79 * TSI148 ASIC register structure overlays and bit field definitions.
83 * PCFS - PCI Configuration Space Registers
84 * LCSR - Local Control and Status Registers
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/openbmc/linux/drivers/phy/mediatek/
H A Dphy-mtk-mipi-dsi-mt8173.c1 // SPDX-License-Identifier: GPL-2.0
7 #include "phy-mtk-io.h"
8 #include "phy-mtk-mipi-dsi.h"
11 #define RG_DSI_LDOCORE_EN BIT(0)
12 #define RG_DSI_CKG_LDOOUT_EN BIT(1)
14 #define RG_DSI_LD_IDX_SEL GENMASK(6, 4)
16 #define RG_DSI_DSICLK_FREQ_SEL BIT(10)
17 #define RG_DSI_LPTX_CLMP_EN BIT(11)
24 #define RG_DSI_LNTx_LDOOUT_EN BIT(0)
25 #define RG_DSI_LNTx_CKLANE_EN BIT(1)
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/openbmc/linux/drivers/usb/typec/tcpm/
H A Dfusb302_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2017 Google, Inc
5 * Fairchild FUSB302 Type-C Chip Driver
13 #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7)
14 #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6)
15 #define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5)
16 #define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4)
17 #define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3)
18 #define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2)
19 #define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1)
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/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dpwrseq.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2013 Realtek Corporation.*/
8 /* Check document WM-20110607-Paul-RTL8188EE_Power_Architecture-R02.vsd
10 * 0: POFF--Power Off
11 * 1: PDN--Power Down
12 * 2: CARDEMU--Card Emulation
13 * 3: ACT--Active Mode
14 * 4: LPS--Low Power State
15 * 5: SUS--Suspend
46 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1) \
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/openbmc/linux/drivers/net/dsa/microchip/
H A Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2024 Microchip Technology Inc.
12 #define KS_PRIO_S 4
14 /* 0 - Operation */
38 #define SWITCH_REVISION_S 4
43 #define PME_ENABLE BIT(1)
44 #define PME_POLARITY BIT(0)
48 #define SW_GIGABIT_ABLE BIT(6)
49 #define SW_REDUNDANCY_ABLE BIT(5)
50 #define SW_AVB_ABLE BIT(4)
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H A Dksz8795_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
22 #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4)
23 #define KSZ8863_PCS_RESET BIT(0)
27 #define SW_NEW_BACKOFF BIT(7)
28 #define SW_GLOBAL_RESET BIT(6)
29 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
30 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
31 #define SW_LINK_AUTO_AGING BIT(0)
35 #define SW_HUGE_PACKET BIT(6)
36 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
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/openbmc/linux/Documentation/input/devices/
H A Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
18 4. Hardware version 1
20 4.2 Native relative mode 4 byte packet format
21 4.3 Native absolute mode 4 byte packet format
25 5.2.1 Parity checking and packet re-synchronization
33 7. Hardware version 4
39 8. Trackpoint (for Hardware version 3 and 4)
51 and version 4. Version 1 is found in "older" laptops and uses 4 bytes per
56 of up to 3 fingers. Hardware version 4 uses 6 bytes per packet, and can
58 4 allows tracking up to 5 fingers.
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/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun9i-a80.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
26 * The CPU PLLs are actually NP clocks, with P being /1 or /4. However
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
36 .enable = BIT(31),
37 .lock = BIT(0),
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
50 .enable = BIT(31),
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/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_hw_autogen.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2023, Intel Corporation. */
4 /* Machine-generated file */
9 #define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4))
10 #define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4))
19 #define PF_FW_ARQLEN_ARQVFE_M BIT(28)
20 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
21 #define PF_FW_ARQLEN_ARQCRIT_M BIT(3
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/openbmc/linux/drivers/gpu/drm/v3d/
H A Dv3d_regs.h1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2017-2018 Broadcom */
30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19)
31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18)
32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17)
33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16)
38 # define V3D_HUB_IDENT1_REV_MASK V3D_MASK(7, 4)
39 # define V3D_HUB_IDENT1_REV_SHIFT 4
44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8)
60 # define V3D_HUB_INT_MMU_WRV BIT(5)
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/openbmc/linux/drivers/platform/x86/intel/pmc/
H A Dmtl.c1 // SPDX-License-Identifier: GPL-2.0
17 * MTL-M SOC-M IOE-M None
18 * MTL-P SOC-M IOE-P None
19 * MTL-S SOC-S IOE-P PCH-S
23 {"PMC", BIT(0)},
24 {"OPI", BIT(1)},
25 {"SPI", BIT(2)},
26 {"XHCI", BIT(3)},
27 {"SPA", BIT(4)},
28 {"SPB", BIT(5)},
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/openbmc/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
18 #define TW5864_EMU_EN_DDR BIT(0)
19 /* Enable bit for Inter module */
20 #define TW5864_EMU_EN_ME BIT(1)
21 /* Enable bit for Sensor Interface module */
22 #define TW5864_EMU_EN_SEN BIT(2)
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/openbmc/linux/sound/soc/fsl/
H A Dfsl_easrc.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/dma/imx-dma.h>
17 #define REG_EASRC_WRFIFO(ctx) (0x000 + 4 * (ctx))
19 #define REG_EASRC_RDFIFO(ctx) (0x010 + 4 * (ctx))
21 #define REG_EASRC_CC(ctx) (0x020 + 4 * (ctx))
23 #define REG_EASRC_CCE1(ctx) (0x030 + 4 * (ctx))
25 #define REG_EASRC_CCE2(ctx) (0x040 + 4 * (ctx))
27 #define REG_EASRC_CIA(ctx) (0x050 + 4 * (ctx))
29 #define REG_EASRC_DPCS0R0(ctx) (0x060 + 4 * (ctx))
30 #define REG_EASRC_DPCS0R1(ctx) (0x070 + 4 * (ctx))
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/openbmc/linux/drivers/gpu/drm/mcde/
H A Dmcde_dsi_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1)
10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2)
11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3)
12 #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4)
13 #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5)
14 #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6)
15 #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7)
16 #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8)
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/openbmc/linux/drivers/media/i2c/ccs/
H A Dccs-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
2 /* Copyright (C) 2019--2020 Intel Corporation */
4 * Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs;
14 #define CCS_FL_16BIT BIT(CCS_FL_BASE)
15 #define CCS_FL_32BIT BIT(CCS_FL_BASE + 1)
16 #define CCS_FL_FLOAT_IREAL BIT(CCS_FL_BASE + 2)
17 #define CCS_FL_IREAL BIT(CCS_FL_BASE + 3)
31 #define CCS_MIPI_CCS_VERSION_MAJOR_SHIFT 4U
60 #define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U
65 #define CCS_R_FRAME_FORMAT_DESCRIPTOR_4(n) ((0x0060 | CCS_FL_32BIT) + (n) * 4)
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