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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos850-clock.yaml20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
71 - description: External reference clock (26 MHz)
87 - description: External reference clock (26 MHz)
105 - description: External reference clock (26 MHz)
123 - description: External reference clock (26 MHz)
141 - description: External reference clock (26 MHz)
165 - description: External reference clock (26 MHz)
183 - description: External reference clock (26 MHz)
201 - description: External reference clock (26 MHz)
225 - description: External reference clock (26 MHz)
[all …]
H A Dsamsung,exynosautov9-clock.yaml20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
70 - description: External reference clock (26 MHz)
86 - description: External reference clock (26 MHz)
104 - description: External reference clock (26 MHz)
122 - description: External reference clock (26 MHz)
142 - description: External reference clock (26 MHz)
164 - description: External reference clock (26 MHz)
186 - description: External reference clock (26 MHz)
206 - description: External reference clock (26 MHz)
226 - description: External reference clock (26 MHz)
H A Dsamsung,exynos7885-clock.yaml20 is an external clock: OSCCLK (26 MHz). This external clock must be defined
64 - description: External reference clock (26 MHz)
80 - description: External reference clock (26 MHz)
102 - description: External reference clock (26 MHz)
128 - description: External reference clock (26 MHz)
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c36 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
40 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
41 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
42 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
43 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
44 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
45 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
46 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
50 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
55 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dlowlevel_init.S208 /* 12MHz */
216 /* 13MHz */
224 /* 19.2MHz */
232 /* 26MHz */
240 /* 38.4MHz */
255 /* 12MHz */
263 /* 13MHz */
271 /* 19.2MHz */
279 /* 26MHz */
287 /* 38.4MHz */
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dhw_data.c32 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
33 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
34 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
35 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
36 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
37 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
38 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
43 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
44 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
45 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
[all …]
/openbmc/linux/drivers/net/wireless/ti/wl12xx/
H A Dwl12xx.h73 WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
74 WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
75 WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
76 WL12XX_REFCLOCK_52 = 3, /* 52 MHz */
77 WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
78 WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
83 WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */
84 WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */
85 WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */
86 WL12XX_TCXOCLOCK_52 = 3, /* 52 MHz */
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c67 { /* 19.2 MHz */
75 { /* 24 MHz */
83 { /* 25 MHz */
91 { /* 26 MHz */
102 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
103 {125, 2, -1, -1, 10, 8, 4}, /* 24 MHz */
104 {40, 0, -1, -1, 10, 8, 4}, /* 25 MHz */
105 {500, 12, -1, -1, 10, 8, 4} /* 26 MHz */
109 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
110 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
45 1e 00 ? looks like operation register; write cmd here, read result from 1f-26
53 26 08 ?
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
91 # 26 chars 29 lines
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
146 * <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz).
[all …]
/openbmc/u-boot/board/bosch/shc/
H A DREADME14 MMC: OMAP SD/MMC: 0 @ 26 MHz, OMAP SD/MMC: 1 @ 26 MHz
79 U-Boot SPL 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18)
82 MPU reference clock runs at 6 MHz
83 Setting MPU clock to 594 MHz
105 U-Boot 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18 +0200)
/openbmc/qemu/include/hw/misc/
H A Daspeed_scu.h102 * 26 2D Engine GCLK clock throttling enable
131 * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)]
148 * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
150 * The default frequency is 792Mhz when CLKIN = 24MHz
161 * 26:24 DRAM configuration setting
162 * 23 Enable 25 MHz reference clock input
268 * 26 Enable eSPI flash mode
271 * 23 Select 25 MHz reference clock input mode
300 #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26)
337 * 28:26 H-PLL Parameters
[all …]
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dmaxim,max8952.yaml62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c19 #define MT7623_PLL_FMAX (2000UL * MHZ)
83 FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
84 FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
85 FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
86 FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
87 FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
88 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
89 FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
90 FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
91 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c20 * XTAL [MHz] 2^(18 - 1)
21 * PLL [MHz] = ------------ * ----------------------
33 /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
63 { 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
64 { 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
72 { 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } },
73 { 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } },
120 /* Test for 40MHz XTAL */ in ar934x_pll_init()
323 printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000); in do_ar934x_showclk()
324 printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000); in do_ar934x_showclk()
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dsata.c19 {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
20 {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
21 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
22 {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
23 {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
24 {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
149 /* TIMER0 runs directly on the 25MHz chrystal */
155 /* TIMER1 runs @ 1MHz */
161 /* TIMER2 runs @ 1MHz */
179 /* The SIC is cascaded off IRQ 26 on the PIC */
[all …]
/openbmc/linux/drivers/phy/ti/
H A Dphy-ti-pipe3.c84 #define MEM_OVRD_HS_RATE BIT(26)
85 #define MEM_OVRD_HS_RATE_SHIFT 26
186 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
187 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
188 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
189 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
190 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
191 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
196 {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
197 {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml68 mediatek,src-ref-clk-mhz:
71 default: 26
94 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
176 mediatek,src-ref-clk-mhz = <26>;
/openbmc/u-boot/drivers/phy/
H A Dti-pipe3-phy.c349 {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
350 {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
351 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
352 {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
353 {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
354 {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
359 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
360 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
361 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
362 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
[all …]
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra30.c34 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
35 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
36 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
37 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
189 { 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */
194 { 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */
201 { 26000000, 624000000, 624, 26, 1, 8 },
206 { 26000000, 600000000, 600, 26, 1, 8 },
209 { 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */
211 { 26000000, 520000000, 520, 26, 1, 8 },
[all …]
/openbmc/linux/include/media/i2c/
H A Dtc358743.h33 u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */
61 * bps pr lane is 823.5 MHz, and can serve as a starting point.
86 /* Reset PHY automatically when TMDS clock passes 21 MHz.
/openbmc/linux/include/linux/mmc/
H A Dmmc.h65 #define MMC_PROGRAM_CID 26 /* adtc R1 */
111 * [31:26] Always 0
139 #define R1_WP_VIOLATION (1 << 26) /* erx, c */
221 /* (CMD16,24,25,26,27) */
353 #define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
354 #define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
357 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
359 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
363 #define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
364 #define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dcpu.c55 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
56 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
57 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
58 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
59 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
60 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
73 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
74 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
75 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
76 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
[all …]

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