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Searched +full:208 +full:mhz (Results 1 – 25 of 119) sorted by relevance

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/openbmc/linux/drivers/cpufreq/
H A Dpxa3xx-cpufreq.c88 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
89 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
90 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
91 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
96 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
97 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
98 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
99 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
100 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Dlowlevel_init.S10 * running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is
11 * 104 MHz and PCLK is 13 MHz.
26 /* Start HCLK PLL for 208 MHz */
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-eth.c79 /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */ in clk_eth_enable()
106 /* switch Esub AXI clock to 208MHz */ in clk_eth_enable()
/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-eth.c79 /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */ in clk_eth_enable()
106 /* switch Esub AXI clock to 208MHz */ in clk_eth_enable()
/openbmc/u-boot/arch/xtensa/cpu/
H A Dcpu.c30 char buf[120], mhz[8]; in print_cpuinfo() local
34 "rsr %1, 208\n" in print_cpuinfo()
37 sprintf(buf, "CPU: Xtensa %s (id: %08x:%08x) at %s MHz\n", in print_cpuinfo()
38 XCHAL_CORE_ID, id0, id1, strmhz(mhz, gd->cpu_clk)); in print_cpuinfo()
/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnxp,s32g2-siul2-pinctrl.yaml80 description: Supported slew rate based on Fmax values (MHz)
81 enum: [83, 133, 150, 166, 208]
113 slew-rate = <208>;
119 slew-rate = <208>;
/openbmc/u-boot/board/toradex/common/
H A Dtdx-cfg-block.c59 [1] = "Colibri PXA270 312MHz",
60 [2] = "Colibri PXA270 520MHz",
61 [3] = "Colibri PXA320 806MHz",
62 [4] = "Colibri PXA300 208MHz",
63 [5] = "Colibri PXA310 624MHz",
64 [6] = "Colibri PXA320 806MHz IT",
65 [7] = "Colibri PXA300 208MHz XT",
66 [8] = "Colibri PXA270 312MHz",
67 [9] = "Colibri PXA270 520MHz",
281 sprintf(message, "Is the module the 312 MHz version? [y/N] "); in get_cfgblock_interactive()
/openbmc/linux/drivers/clk/renesas/
H A Dr8a7792-cpg-mssr.c92 DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
165 * 14 13 19 (MHz) *1 *2
183 { 1, 208, 106, 200 },
184 { 1, 208, 88, 200 },
189 { 2, 208, 106, 200 },
190 { 2, 208, 88, 200 },
H A Dr8a7742-cpg-mssr.c108 DEF_MOD("msiof1", 208, R8A7742_CLK_MP),
213 * 14 13 19 (MHz) *1 *1
232 { 1, 208, 106, },
233 { 1, 208, 88, },
238 { 2, 208, 106, },
239 { 2, 208, 88, },
H A Dr8a7743-cpg-mssr.c102 DEF_MOD("msiof1", 208, R8A7743_CLK_MP),
207 * 14 13 19 (MHz) *1 *1
226 { 1, 208, 106, },
227 { 1, 208, 88, },
232 { 2, 208, 106, },
233 { 2, 208, 88, },
H A Dr8a7790-cpg-mssr.c119 DEF_MOD("msiof1", 208, R8A7790_CLK_MP),
222 * 14 13 19 (MHz) *1 *1
239 { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
240 { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
H A Dr8a7791-cpg-mssr.c112 DEF_MOD("msiof1", 208, R8A7791_CLK_MP),
220 * 14 13 19 (MHz) *1 *1
237 { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
238 { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
H A Dr8a7745-cpg-mssr.c100 DEF_MOD("msiof1", 208, R8A7745_CLK_MP),
191 * 14 13 19 (MHz) *1 *2
206 { 1, 208, 88, 200 },
209 { 2, 208, 88, 200 },
H A Dr8a7794-cpg-mssr.c107 DEF_MOD("msiof1", 208, R8A7794_CLK_MP),
201 * 14 13 19 (MHz) *1 *2
214 { 1, 208, 88, 200 },
217 { 2, 208, 88, 200 },
/openbmc/u-boot/drivers/clk/renesas/
H A Dr8a7792-cpg-mssr.c94 DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
161 * 14 13 19 (MHz) *1 *2
179 { 1, 208, 106, 200 },
180 { 1, 208, 88, 200 },
185 { 2, 208, 106, 200 },
186 { 2, 208, 88, 200 },
H A Dr8a7790-cpg-mssr.c121 DEF_MOD("msiof1", 208, R8A7790_CLK_MP),
218 * 14 13 19 (MHz) *1 *1
235 { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
236 { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
H A Dr8a7791-cpg-mssr.c112 DEF_MOD("msiof1", 208, R8A7791_CLK_MP),
214 * 14 13 19 (MHz) *1 *1
231 { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
232 { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
H A Dr8a7794-cpg-mssr.c109 DEF_MOD("msiof1", 208, R8A7794_CLK_MP),
197 * 14 13 19 (MHz) *1 *2
210 { 1, 208, 88, 200 },
213 { 2, 208, 88, 200 },
/openbmc/u-boot/drivers/mmc/
H A DKconfig104 frequency can go up to 208MHz (SDR104)
112 frequency can go up to 208MHz (SDR104)
119 200MHz. This mode requires tuning the IO.
125 200MHz. This mode requires tuning the IO.
131 200MHz. This mode requires tuning the IO.
138 200MHz. This mode requires tuning the IO.
/openbmc/linux/drivers/staging/rtl8192u/ieee80211/
H A Drtl819x_HTProc.c14 { {13, 26, 39, 52, 78, 104, 117, 130, 26, 52, 78, 104, 156, 208, 234, 260,
15 39, 78, 117, 234, 312, 351, 390, 52, 104, 156, 208, 312, 416, 468, 520,
16 0, 78, 104, 130, 117, 156, 195, 104, 130, 130, 156, 182, 182, 208, 156, 195,
17 195, 234, 273, 273, 312, 130, 156, 181, 156, 181, 208, 234, 208, 234, 260, 260,
18 286, 195, 234, 273, 234, 273, 312, 351, 312, 351, 390, 390, 429}, // Long GI, 20MHz
23 318, 217, 260, 303, 260, 303, 347, 390, 347, 390, 433, 433, 477} }, // Short GI, 20MHz
28 594, 405, 486, 567, 486, 567, 648, 729, 648, 729, 810, 810, 891}, // Long GI, 40MHz
33 660, 450, 540, 630, 540, 630, 720, 810, 720, 810, 900, 900, 990} } // Short GI, 40MHz
70 // 40MHz channel support in HTUpdateDefaultSetting()
73 // CCK rate support in 40MHz channel in HTUpdateDefaultSetting()
[all …]
/openbmc/linux/samples/bpf/
H A Dcpustat_kern.c16 * 208MHz, 432MHz, 729MHz, 960MHz, 1200MHz
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dhw_data.c32 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
33 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
34 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
35 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
36 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
37 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
38 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
43 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
44 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
45 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dmacmodes.c36 /* 512x384, 60Hz, Non-Interlaced (15.67 MHz dot clock) */
40 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
44 /* 640x480, 67Hz, Non-Interlaced (30.0 MHz dotclock) */
48 /* 640x870, 75Hz (portrait), Non-Interlaced (57.28 MHz dot clock) */
52 /* 800x600, 56 Hz, Non-Interlaced (36.00 MHz dotclock) */
56 /* 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock) */
60 /* 800x600, 72 Hz, Non-Interlaced (50.00 MHz dotclock) */
64 /* 800x600, 75 Hz, Non-Interlaced (49.50 MHz dotclock) */
68 /* 832x624, 75Hz, Non-Interlaced (57.6 MHz dotclock) */
69 "mac13", 75, 832, 624, 17362, 208, 48, 39, 1, 64, 3,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller.yaml93 - for eMMC, the maximum supported frequency is 200MHz,
95 frequency of 208MHz,
97 384MHz.

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