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/openbmc/linux/drivers/gpu/drm/etnaviv/
H A Dstate_hi.xml.h6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
10 The rules-ng-ng source files this header was generated from are:
11 - state.xml ( 27198 bytes, from 2022-04-22 10:35:24)
12 - common.xml ( 35468 bytes, from 2020-10-28 12:56:03)
13 - common_3d.xml ( 15058 bytes, from 2020-10-28 12:56:03)
14 - state_hi.xml ( 34804 bytes, from 2022-12-02 09:06:28)
15 - copyright.xml ( 1597 bytes, from 2020-10-28 12:56:03)
16 - state_2d.xml ( 51552 bytes, from 2020-10-28 12:56:03)
[all …]
/openbmc/linux/Documentation/networking/device_drivers/ethernet/marvell/
H A Docteontx2.rst1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
7 Copyright (c) 2020 Marvell International Ltd.
12 - `Overview`_
13 - `Drivers`_
14 - `Basic packet flow`_
15 - `Devlink health reporters`_
16 - `Quality of service`_
23 PCI-compatible physical and virtual functions. Each functional block
31 - Network pool or buffer allocator (NPA)
32 - Network interface controller (NIX)
[all …]
/openbmc/linux/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/
H A Dsun8i_a83t_mipi_csi2_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2020 Kévin L'hôpital <kevin.lhopital@bootlin.com>
4 * Copyright 2020-2022 Bootlin
40 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_CRC_ERR_VC0 BIT(12)
42 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_FRM_SEQ_ERR_VC2 BIT(10)
65 #define SUN8I_A83T_MIPI_CSI2_INT_STA1_DT_ERR_VC0 BIT(12)
67 #define SUN8I_A83T_MIPI_CSI2_INT_STA1_ECC_ERR1_VC2 BIT(10)
95 #define SUN8I_A83T_MIPI_CSI2_INT_MSK0_CRC_ERR_VC0 BIT(12)
97 #define SUN8I_A83T_MIPI_CSI2_INT_MSK0_FRM_SEQ_ERR_VC2 BIT(10)
112 #define SUN8I_A83T_MIPI_CSI2_INT_MSK1_DT_ERR_VC0 BIT(12)
[all …]
/openbmc/linux/include/dt-bindings/interconnect/
H A Dqcom,sm8250.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
21 #define A1NOC_SNOC_SLV 10
23 #define SLAVE_SERVICE_A1NOC 12
35 #define MASTER_UFS_CARD 10
37 #define SLAVE_ANOC_PCIE_GEM_NOC 12
53 #define SLAVE_RBCPR_CX_CFG 10
55 #define SLAVE_RBCPR_MX_CFG 12
110 #define MASTER_SNOC_SF_MEM_NOC 10
112 #define SLAVE_LLCC 12
[all …]
H A Dqcom,sm8150.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
30 #define MASTER_PCIE 10
32 #define MASTER_QDSS_ETR 12
57 #define SLAVE_CDSP_CFG 10
59 #define SLAVE_RBCPR_MMCX_CFG 12
116 #define MASTER_SNOC_SF_MEM_NOC 10
118 #define SLAVE_MSS_PROC_MS_MPU_CFG 12
137 #define SLAVE_MNOC_SF_MEM_NOC 10
139 #define SLAVE_SERVICE_MNOC 12
[all …]
H A Dqcom,sc7180.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
49 #define SLAVE_CAMERA_NRT_THROTTLE_CFG 10
51 #define SLAVE_CLK_CTL 12
107 #define SLAVE_GEM_NOC_SNOC 10
109 #define SLAVE_SERVICE_GEM_NOC 12
124 #define SLAVE_SERVICE_MNOC 10
136 #define SLAVE_SERVICE_NPU_NOC 10
153 #define SLAVE_PIMEM 10
155 #define SLAVE_QDSS_STM 12
H A Dqcom,sm8450.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
29 #define MASTER_SDCC_2 10
31 #define SLAVE_SERVICE_A2NOC 12
50 #define SLAVE_RBCPR_MXA_CFG 10
52 #define SLAVE_CRYPTO_0_CFG 12
106 #define MASTER_SNOC_SF_MEM_NOC 10
108 #define SLAVE_LLCC 12
140 #define MASTER_VIDEO_V_PROC 10
142 #define SLAVE_MNOC_SF_MEM_NOC 12
H A Dqcom,sm8350.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
32 #define MASTER_UFS_CARD 10
34 #define SLAVE_ANOC_PCIE_GEM_NOC 12
47 #define SLAVE_RBCPR_CX_CFG 10
49 #define SLAVE_RBCPR_MX_CFG 12
113 #define MASTER_SNOC_SF_MEM_NOC 10
115 #define SLAVE_MCDMA_MS_MPU_CFG 12
149 #define SLAVE_MNOC_HF_MEM_NOC 10
151 #define SLAVE_SERVICE_MNOC 12
H A Dqcom,msm8939.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (c) 2020, Linaro Ltd.
22 #define SLAVE_SRVC_SNOC 10
24 #define SNOC_BIMC_1_MAS 12
62 #define PCNOC_INT_1 10
64 #define PCNOC_MAS_1 12
/openbmc/linux/include/dt-bindings/clock/
H A Dmt8167-clk.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2020 MediaTek Inc.
4 * Copyright (c) 2020 BayLibre, SAS.
13 #include <dt-bindings/clock/mt8516-clk.h>
34 #define CLK_TOP_TVDPLL_D2 (CLK_TOP_NR_CLK + 10)
36 #define CLK_TOP_TVDPLL_D8 (CLK_TOP_NR_CLK + 12)
89 #define CLK_MM_DISP_OVL0 10
91 #define CLK_MM_DISP_RDMA1 12
H A Dmicrochip,mpfs-clock.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
4 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
21 #define CLK_MMUART2 10
23 #define CLK_MMUART4 12
62 #define CLK_CCC_PLL1_OUT2 10
65 #define CLK_CCC_DLL0_OUT0 12
H A Dbt1-ccu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 * Baikal-T1 CCU clock indices
26 #define CCU_AXI_SRAM_CLK 10
38 #define CCU_SYS_HWA_CLK 10
40 #define CCU_SYS_I2C1_CLK 12
H A Dqcom,gcc-sdx55.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
4 * Copyright (c) 2020, Linaro Ltd.
17 #define GCC_BLSP1_QUP1_I2C_APPS_CLK 10
19 #define GCC_BLSP1_QUP1_SPI_APPS_CLK 12
106 #define GCC_TCSR_PCIE_BCR 10
108 #define GCC_USB3_PHY_BCR 12
H A Dqcom,gcc-sm8350.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2021, Linaro Limited
20 #define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK 10
24 #define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 12
224 #define GCC_PCIE_1_LINK_DOWN_BCR 10
226 #define GCC_PCIE_1_PHY_BCR 12
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
4 * Copyright (c) 2020 Engicam srl
5 * Copyright (c) 2020 Amarula Solutions(India)
8 /dts-v1/;
10 #include "stm32mp157a-microgea-stm32mp1.dtsi"
11 #include "stm32mp15-pinctrl.dtsi"
12 #include "stm32mp15xxaa-pinctrl.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "engicam,microgea-stm32mp1-microdev2.0-of7",
[all …]
/openbmc/linux/drivers/net/can/dev/
H A Dlength.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2012, 2020 Oliver Hartkopp <socketcan@hartkopp.net>
11 8, 12, 16, 20, 24, 32, 48, 64
22 0, 1, 2, 3, 4, 5, 6, 7, 8, /* 0 - 8 */
23 9, 9, 9, 9, /* 9 - 12 */
24 10, 10, 10, 10, /* 13 - 16 */
25 11, 11, 11, 11, /* 17 - 20 */
26 12, 12, 12, 12, /* 21 - 24 */
27 13, 13, 13, 13, 13, 13, 13, 13, /* 25 - 32 */
28 14, 14, 14, 14, 14, 14, 14, 14, /* 33 - 40 */
[all …]
/openbmc/openbmc-test-automation/pldm/
H A Dtest_pldm_bios.robot26 # "Response": "2020-11-07 07:10:10"
34 # Date format example: 2022-10-12 16:31:17
36 # Example : ['2022-10-12', '16:31:17']
54 # 2020-11-25 07:34:30
57 ${upgrade_date}= Evaluate re.sub(r'-* *:*', "", '${date}') modules=re
60 ${upgrade_time}= Evaluate re.sub(r'-* *:*', "", '${time}') modules=re
98 # pldmtool bios GetBIOSAttributeCurrentValueByHandle -a pvm_fw_boot_side
106 ${cur_attr}= Pldmtool bios GetBIOSAttributeCurrentValueByHandle -a ${i}
118 ${pldm_output}= Pldmtool bios GetBIOSTable --type AttributeTable
123 Sleep 10s
[all …]
/openbmc/linux/drivers/pinctrl/visconti/
H A Dpinctrl-tmpv7700.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020 TOSHIBA CORPORATION
4 * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation
5 * Copyright (c) 2020 Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
13 #include "pinctrl-common.h"
52 VISCONTI_PIN(PINCTRL_PIN(5, "gpio5"), REG_IO_DSEL5, 12,
62 VISCONTI_PIN(PINCTRL_PIN(10, "gpio10"), REG_IO_DSEL6, 0,
66 VISCONTI_PIN(PINCTRL_PIN(12, "gpio12"), REG_IO_DSEL6, 8,
67 REG_IO_PUDE2, REG_IO_PUDSEL2, 10),
68 VISCONTI_PIN(PINCTRL_PIN(13, "gpio13"), REG_IO_DSEL6, 12,
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dmeson-mx-sdhc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2020 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
19 #define MESON_SDHC_SEND_DATA_DIR BIT(10)
21 #define MESON_SDHC_SEND_R1B BIT(12)
28 #define MESON_SDHC_CTRL_PACK_LEN GENMASK(12, 4)
40 #define MESON_SDHC_STAT_RXFIFO_CNT GENMASK(12, 6)
56 #define MESON_SDHC_PDMA_RD_BURST GENMASK(14, 10)
83 #define MESON_SDHC_ICTL_DAT1_IRQ BIT(10)
85 #define MESON_SDHC_ICTL_RXFIFO_FULL BIT(12)
102 #define MESON_SDHC_ISTA_DAT1_IRQ BIT(10)
[all …]
/openbmc/linux/arch/riscv/kernel/
H A Djump_label.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020 Emil Renner Berthing
24 long offset = jump_entry_target(entry) - jump_entry_code(entry); in arch_jump_label_transform()
26 if (WARN_ON(offset & 1 || offset < -524288 || offset >= 524288)) in arch_jump_label_transform()
30 (((u32)offset & GENMASK(19, 12)) << (12 - 12)) | in arch_jump_label_transform()
31 (((u32)offset & GENMASK(11, 11)) << (20 - 11)) | in arch_jump_label_transform()
32 (((u32)offset & GENMASK(10, 1)) << (21 - 1)) | in arch_jump_label_transform()
33 (((u32)offset & GENMASK(20, 20)) << (31 - 20)); in arch_jump_label_transform()
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/mcelog/mce-test/
H A D0001-gcov_merge.py-scov_merge.py-switch-to-python3.patch3 Date: Mon, 13 Apr 2020 07:12:44 +0000
8 Upstream-Status: Pending
10 Signed-off-by: Mingli Yu <mingli.yu@windriver.com>
11 ---
12 tools/scripts/gcov_merge.py | 12 ++++++------
13 tools/scripts/scov_merge.py | 12 ++++++------
14 2 files changed, 12 insertions(+), 12 deletions(-)
16 diff --git a/tools/scripts/gcov_merge.py b/tools/scripts/gcov_merge.py
18 --- a/tools/scripts/gcov_merge.py
20 @@ -1,4 +1,4 @@
[all …]
/openbmc/linux/include/dt-bindings/memory/
H A Dmt8167-larb-port.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2020 MediaTek Inc.
4 * Copyright (c) 2020 BayLibre, SAS
11 #include <dt-bindings/memory/mtk-memory-port.h>
38 #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 10)
40 #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 12)
/openbmc/qemu/include/hw/misc/
H A Dnpcm7xx_gcr.h4 * Copyright 2020 Google LLC
24 * 12: SPI0 powered by VSBV3 at 1.8V
26 * 10: BSP alternative pins.
29 * 6: HI-Z state control.
35 #define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12)
37 #define NPCM7XX_PWRON_STRAP_BSPA BIT(10)
70 #define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
/openbmc/linux/tools/perf/Documentation/
H A Dsecurity.txt6 https://www.kernel.org/doc/html/latest/admin-guide/perf-security.html
15 1. Download selinux-policy SRPM package (e.g. selinux-policy-3.14.4-48.fc31.src.rpm on FC31)
18 # rpm -Uhv selinux-policy-3.14.4-48.fc31.src.rpm
22 # rpmbuild -bp selinux-policy.spec
24 3. Place patch below at rpmbuild/BUILD/selinux-policy-b86eaaf4dbcf2d51dd4432df7185c0eaf3cbcc02
27 # patch -p1 < selinux-policy-perf-events-perfmon.patch
30 # cat selinux-policy-perf-events-perfmon.patch
31 diff -Nura a/policy/flask/access_vectors b/policy/flask/access_vectors
32 --- a/policy/flask/access_vectors 2020-02-04 18:19:53.000000000 +0300
33 +++ b/policy/flask/access_vectors 2020-02-28 23:37:25.000000000 +0300
[all …]
/openbmc/linux/drivers/net/ethernet/mellanox/mlxbf_gige/
H A Dmlxbf_gige_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
5 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
96 /* ipg_size default value for 1G is fixed by HW to 11 + End = 12.
97 * So for 100M it is 12 * 10 - 1 = 119
98 * For 10M, it is 12 * 100 - 1 = 1199

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