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/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dhw_data.c32 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
33 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
34 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
35 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
36 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
37 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
38 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
43 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
44 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
45 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c36 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
40 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
41 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
42 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
43 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
44 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
45 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
46 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
50 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
55 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
[all …]
/openbmc/linux/drivers/clk/spear/
H A Dspear1340_clock.c21 #define SPEAR1340_HCLK_SRC_SEL_MASK 1
28 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
48 #define SPEAR1340_SPDIF_CLK_MASK 1
53 #define SPEAR1340_GPT_CLK_MASK 1
61 #define SPEAR1340_C3_CLK_MASK 1
62 #define SPEAR1340_C3_CLK_SHIFT 1
65 #define SPEAR1340_GMAC_PHY_CLK_MASK 1
83 #define SPEAR1340_I2S_REF_SEL_MASK 1
128 #define SPEAR1340_SYSROM_CLK_ENB 1
139 #define SPEAR1340_DDR_CORE_CLK_ENB 1
[all …]
H A Dspear1310_clock.c21 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1
43 #define SPEAR1310_GPT_APB_VAL 1
44 #define SPEAR1310_GPT_CLK_MASK 1
50 #define SPEAR1310_UART_CLK_OSC24_VAL 1
56 #define SPEAR1310_AUX_CLK_SYNT_VAL 1
59 #define SPEAR1310_C3_CLK_MASK 1
60 #define SPEAR1310_C3_CLK_SHIFT 1
65 #define SPEAR1310_GMAC_PHY_CLK_MASK 1
68 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1
83 #define SPEAR1310_I2S_REF_SEL_MASK 1
[all …]
/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
64 # 7 chars 1 lines
[all …]
/openbmc/u-boot/board/freescale/common/
H A Didt8t49n222a_serdes_clk.c16 ret = i2c_read(idt_addr, 0x17, 1, &val, 1); in check_pll_status()
27 return -1; in check_pll_status()
43 ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1); in set_serdes_refclk()
55 if (serdes_num != 1 && serdes_num != 2) { in set_serdes_refclk()
56 debug("serdes_num should be 1 for SerDes1 and" in set_serdes_refclk()
58 return -1; in set_serdes_refclk()
64 debug("Only one refclk at 122.88MHz is not supported." in set_serdes_refclk()
65 " Please set both refclk1 & refclk2 to 122.88MHz" in set_serdes_refclk()
66 " or both not to 122.88MHz.\n"); in set_serdes_refclk()
67 return -1; in set_serdes_refclk()
[all …]
/openbmc/linux/drivers/clk/mvebu/
H A Dmv98dx3236.c25 * 0 = 400 MHz 400 MHz 800 MHz
26 * 2 = 667 MHz 667 MHz 2000 MHz
27 * 3 = 800 MHz 800 MHz 1600 MHz
34 * 1 = 667 MHz 667 MHz 2000 MHz
35 * 2 = 400 MHz 400 MHz 400 MHz
36 * 3 = 800 MHz 800 MHz 800 MHz
37 * 5 = 800 MHz 400 MHz 800 MHz
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
98 {0, 1}, {3, 1}, {1, 1}, {1, 1},
99 {0, 1}, {1, 1}, {0, 1}, {0, 1},
[all …]
H A Darmada-375.c29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
93 {0, 1}, {0, 1}, {0, 1}, {0, 1},
94 {0, 1}, {0, 1}, {1, 2}, {0, 1},
95 {0, 1}, {0, 1}, {0, 1}, {0, 1},
96 {0, 1}, {0, 1}, {0, 1}, {1, 2},
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/
H A Dtypes.h21 #define SC_10MHZ 10000000U /* 10MHz */
22 #define SC_20MHZ 20000000U /* 20MHz */
23 #define SC_25MHZ 25000000U /* 25MHz */
24 #define SC_27MHZ 27000000U /* 27MHz */
25 #define SC_40MHZ 40000000U /* 40MHz */
26 #define SC_45MHZ 45000000U /* 45MHz */
27 #define SC_50MHZ 50000000U /* 50MHz */
28 #define SC_60MHZ 60000000U /* 60MHz */
29 #define SC_66MHZ 66666666U /* 66MHz */
30 #define SC_74MHZ 74250000U /* 74.25MHz */
[all …]
/openbmc/linux/arch/x86/kernel/
H A Dtsc_msr.c22 * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
24 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
25 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
33 * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
34 * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
80 * 000: 100 * 5 / 6 = 83.3333 MHz
81 * 001: 100 * 1 / 1 = 100.0000 MHz
82 * 010: 100 * 4 / 3 = 133.3333 MHz
83 * 011: 100 * 7 / 6 = 116.6667 MHz
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dcpu.c45 * T20: 1 GHz
55 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
56 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
57 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
58 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
59 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
60 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
73 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
74 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
75 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dopp2xxx.h20 * 2430 (iva2.1, NOdsp, mdm)
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
48 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
68 /* 2430 Ratio's, 2430-Ratio Config 1 */
103 #define RB_CLKSEL_L3 (1 << 0)
104 #define RB_CLKSEL_L4 (1 << 5)
105 #define RB_CLKSEL_USB (1 << 25)
109 #define RB_CLKSEL_MPU (1 << 0)
111 #define RB_CLKSEL_DSP (1 << 0)
112 #define RB_CLKSEL_DSP_IF (1 << 5)
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dlowlevel_init.S35 .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
160 .word (WKUP_RSM << 1)
199 /* DPLL(1-4) PARAM TABLES */
208 /* 12MHz */
216 /* 13MHz */
224 /* 19.2MHz */
232 /* 26MHz */
240 /* 38.4MHz */
255 /* 12MHz */
263 /* 13MHz */
[all …]
/openbmc/linux/arch/mips/txx9/rbtx4927/
H A Dsetup.c75 writeb(1, rbtx4927_pcireset_addr); in tx4927_pci_setup()
93 writeb(1, rbtx4927_pcireset_addr); in tx4927_pci_setup()
122 writeb(1, rbtx4927_pcireset_addr); in tx4937_pci_setup()
140 writeb(1, rbtx4927_pcireset_addr); in tx4937_pci_setup()
164 gpio_direction_output(15, 1); in rbtx4927_gpio_init()
190 writeb(1, rbtx4927_softresetlock_addr); in toshiba_rbtx4927_restart()
193 while (!(readb(rbtx4927_softresetlock_addr) & 1)) in toshiba_rbtx4927_restart()
197 writeb(1, rbtx4927_softreset_addr); in toshiba_rbtx4927_restart()
231 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. in rbtx4927_clock_init()
234 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). in rbtx4927_clock_init()
[all …]
/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_mipi_dsi.c31 #define MHZ(v) ((u32)((v) * 1000000U)) macro
102 { MHZ(80), 0x00 }, { MHZ(90), 0x10 }, { MHZ(100), 0x20 },
103 { MHZ(110), 0x30 }, { MHZ(120), 0x01 }, { MHZ(130), 0x11 },
104 { MHZ(140), 0x21 }, { MHZ(150), 0x31 }, { MHZ(160), 0x02 },
105 { MHZ(170), 0x12 }, { MHZ(180), 0x22 }, { MHZ(190), 0x32 },
106 { MHZ(205), 0x03 }, { MHZ(220), 0x13 }, { MHZ(235), 0x23 },
107 { MHZ(250), 0x33 }, { MHZ(275), 0x04 }, { MHZ(300), 0x14 },
108 { MHZ(325), 0x25 }, { MHZ(350), 0x35 }, { MHZ(400), 0x05 },
109 { MHZ(450), 0x16 }, { MHZ(500), 0x26 }, { MHZ(550), 0x37 },
110 { MHZ(600), 0x07 }, { MHZ(650), 0x18 }, { MHZ(700), 0x28 },
[all …]
/openbmc/linux/drivers/media/usb/dvb-usb-v2/
H A Daf9035.h56 u8 dual_mode:1;
57 u8 no_read:1;
75 { 0x67, 0x63, 1 },
81 16384000, /* 16.38 MHz */
82 20480000, /* 20.48 MHz */
83 36000000, /* 36.00 MHz */
84 30000000, /* 30.00 MHz */
85 26000000, /* 26.00 MHz */
86 28000000, /* 28.00 MHz */
87 32000000, /* 32.00 MHz */
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dtuner-types.c65 { 16 * 140.25 /*MHz*/, 0x8e, 0x02, },
66 { 16 * 463.25 /*MHz*/, 0x8e, 0x04, },
81 { 16 * 140.25 /*MHz*/, 0x8e, 0xa0, },
82 { 16 * 463.25 /*MHz*/, 0x8e, 0x90, },
97 { 16 * 157.25 /*MHz*/, 0x8e, 0xa0, },
98 { 16 * 451.25 /*MHz*/, 0x8e, 0x90, },
107 .cb_first_if_lower_freq = 1,
114 { 16 * 168.25 /*MHz*/, 0x8e, 0xa7, },
115 { 16 * 447.25 /*MHz*/, 0x8e, 0x97, },
124 .cb_first_if_lower_freq = 1,
[all …]
/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME23 ECC), up to 1333 MHz data rate
46 - 32 KB, 8-way, level 1 instruction cache (L1 ICache)
47 - 32 KB, 8-way, level 1 data cache (L1 DCache)
73 Core MHz/CCB MHz/DDR(MT/s)
74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
81 1. NOR Flash
93 1. NOR Flash
[all …]
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_mipi_dsi_common.c17 #define MHZ (1000 * 1000) macro
18 #define FIN_HZ (24 * MHZ)
20 #define DFIN_PLL_MIN_HZ (6 * MHZ)
21 #define DFIN_PLL_MAX_HZ (12 * MHZ)
23 #define DFVCO_MIN_HZ (500 * MHZ)
24 #define DFVCO_MAX_HZ (1000 * MHZ)
38 DSIM_LANE_CLOCK = (1 << 0),
39 DSIM_LANE_DATA0 = (1 << 1),
40 DSIM_LANE_DATA1 = (1 << 2),
41 DSIM_LANE_DATA2 = (1 << 3),
[all …]
/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c70 divf_val = 1 + divfi + divff / (1 << 24); in decode_frac_pll()
72 pllout = pll_refclk / (divr_val + 1) * 8 * divf_val / in decode_frac_pll()
73 ((divq_val + 1) * 2); in decode_frac_pll()
75 return pllout / (pllout_div + 1); in decode_frac_pll()
141 div = 1; in decode_sscg_pll()
145 div = 1; in decode_sscg_pll()
150 div = 1; in decode_sscg_pll()
241 pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) / in decode_sscg_pll()
242 (divr2 + 1) * (divf2 + 1) / (divq + 1); in decode_sscg_pll()
244 return pllout / (pllout_div + 1) / div; in decode_sscg_pll()
[all …]
/openbmc/linux/Documentation/userspace-api/media/dvb/
H A Dfe-bandwidth-t.rst10 :header-rows: 1
14 - .. row 1
30 - .. _BANDWIDTH-1-712-MHZ:
34 - 1.712 MHz
38 - .. _BANDWIDTH-5-MHZ:
42 - 5 MHz
46 - .. _BANDWIDTH-6-MHZ:
50 - 6 MHz
54 - .. _BANDWIDTH-7-MHZ:
58 - 7 MHz
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c62 CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
64 1000, OSC-1, -1, -1, 10, 8, 4};
67 { /* 19.2 MHz */
68 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
69 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
70 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
71 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
72 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
73 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
75 { /* 24 MHz */
[all …]
/openbmc/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_vangogh.h45 uint16_t Freq; // in MHz
50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
62 #define WM_RETRAINING 1
124 //Freq in MHz
156 #define THROTTLER_STATUS_BIT_FPPT 1
168 uint16_t GfxclkFrequency; //[MHz]
169 uint16_t SocclkFrequency; //[MHz]
170 uint16_t VclkFrequency; //[MHz]
171 uint16_t DclkFrequency; //[MHz]
[all …]
/openbmc/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-capacity.txt6 1 - Introduction
38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
61 Example 1 (ARM 64-bit, 6-cpu system, two clusters):
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
[all …]

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