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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dv3-v360epc-pci.txt11 second the configuration area register space, 16MB
18 each be exactly 256MB (0x10000000) in size.
22 be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB,
23 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
50 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
59 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
63 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
67 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
71 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2.h16 #define CFG_BAR_SIZE 0x10000000ull /* 256MB */
18 #define MSIX_BAR_SIZE 0x4000ull /* 16KB */
21 #define CFG_SIZE 0x8000000ull /* 96MB CFG + 32MB DBG*/
22 #define CFG_REGION_SIZE 0xC000000ull /* 192MB */
24 #define STM_FLASH_BASE_ADDR 0x1000007FF4000000ull /* Not 256MB aligned */
25 #define STM_FLASH_ALIGNED_OFF 0x4000000ull /* 256 MB alignment */
26 #define STM_FLASH_SIZE 0x2000000ull /* 32MB */
29 #define SPI_FLASH_SIZE 0x1000000ull /* 16MB */
38 #define BAR0_RSRVD_SIZE 0x1000000ull /* 16MB */
41 #define SRAM_SIZE 0x3000000ull /* 48MB */
[all …]
/openbmc/linux/arch/alpha/kernel/
H A Dcore_mcpcia.c27 * NOTE: Herein lie back-to-back mb instructions. They are magic.
72 * 23:16 bus number (8 bits = 128 possible buses)
104 mb(); in conf_read()
108 mb(); in conf_read()
113 mb(); in conf_read()
117 mb(); in conf_read()
118 mb(); /* magic */ in conf_read()
123 mb(); in conf_read()
126 mb(); in conf_read()
148 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb(); in conf_write()
[all …]
H A Dsys_alcor.c42 mb(); in alcor_update_irq_hw()
48 alcor_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); in alcor_enable_irq()
54 alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); in alcor_disable_irq()
63 *(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb(); in alcor_mask_and_ack_irq()
64 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_mask_and_ack_irq()
73 *(vuip)GRU_INT_CLEAR = 0x80000000; mb(); in alcor_isa_mask_and_ack_irq()
74 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_isa_mask_and_ack_irq()
103 handle_irq(16 + i); in alcor_device_interrupt()
116 *(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */ in alcor_init_irq()
117 *(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */ in alcor_init_irq()
[all …]
/openbmc/u-boot/arch/mips/mach-bmips/
H A DKconfig134 Broadcom BCM968380GERG reference board with BCM68380 SoC with 512 MB
135 of RAM and 128 MB of flash (nand).
145 Comtrend AR-5315u boards have a BCM6318 SoC with 64 MB of RAM and 16
146 MB of flash (SPI).
156 Comtrend AR-5387un boards have a BCM6328 SoC with 64 MB of RAM and 16
157 MB of flash (SPI).
167 Comtrend CT-5361 boards have a BCM6348 SoC with 16 MB of RAM and 4 MB
178 Comtrend VR-3032u boards have a BCM63268 SoC with 64 MB of RAM and
179 128 MB of flash (NAND).
189 Comtrend WAP-5813n boards have a BCM6369 SoC with 64 MB of RAM and
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/hddtemp/hddtemp/
H A Dhddtemp.db70 "FUJITSU MHT2030AC" 194 C "Fujitsu Mobile 30GB, 2MB, 4200RPM (automotive)"
79 "FUJITSU MHU2100AT" 194 C "Fujitsu MHU2100AT 100GB, 8MB (4200RPM)"
110 "HDS722516VLAT[28]0" 194 C "Hitachi Deskstar 7K250 160GB 2/8MB cache"
111 "HDS722525VLAT80" 194 C "Hitachi Deskstar 7K250 200/250GB, 7200RPM, 8MB, Parallel-ATA"
113 "HDS722540VLAT20" 194 C "Hitachi Deskstar 7K250, 40GB, 7200RPM, 2MB cache"
115 "HDS724040KLSA80" 194 C "Hitachi Deskstar 7K250 400GB, 7200RPM, 8MB, Serial-ATA"
118 "HDS722525VLSA80" 194 C "Hitachi Deskstar 7K250 250GB, 7200RPM, 8MB, SATA"
125 "HDT7225(16|25)DLAT80" 194 C "Hitachi Deskstar T7K250 series, 7200RPM, 8MB, PATA"
128 "HDT725050VLA360" 194 C "Hitachi Deskstar T7K500 500GB, 7200RPM, 16MB, SATA II"
133 "HTS424040M9AT00" 194 C "Hitachi Travelstar 4K40 40GB 2MB cache (4200RPM)"
[all …]
/openbmc/linux/Documentation/arch/x86/x86_64/
H A Dmm.rst20 from TB to GB and then MB/KB.
22 - "16M TB" might look weird at first sight, but it's an easier way to visualize size
23 notation than "16 EB", which few will recognize at first sight as 16 exabytes.
35 …0000800000000000 | +128 TB | ffff7fffffffffff | ~16M TB | ... huge, almost 64 bits wide hole of…
51 ffffec0000000000 | -20 TB | fffffbffffffffff | 16 TB | KASAN shadow memory
65 …ffffffff80000000 | -2 GB | ffffffff9fffffff | 512 MB | kernel text mapping, mapped to physic…
66 ffffffff80000000 |-2048 MB | | |
67 ffffffffa0000000 |-1536 MB | fffffffffeffffff | 1520 MB | module mapping space
68 ffffffffff000000 | -16 MB | | |
69 …FIXADDR_START | ~-11 MB | ffffffffff5fffff | ~0.5 MB | kernel-internal fixmap range, variable s…
[all …]
/openbmc/u-boot/include/configs/
H A Dsbc8548.h120 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
128 * Two banks, one 8MB the other 64MB, using the CFI driver.
130 * CS0 the 8MB boot flash, and CS6 the 64MB flash.
133 * ec00_0000 efff_ffff 64MB SODIMM
134 * ff80_0000 ffff_ffff 8MB soldered flash
137 * ef80_0000 efff_ffff 8MB soldered flash
138 * fc00_0000 ffff_ffff 64MB SODIMM
141 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
147 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
150 * 0 4 8 12 16 20 24 28
[all …]
/openbmc/linux/arch/microblaze/kernel/
H A Dhead.S147 * kernel initialization. This maps the first 16 MBytes of memory 1:1
184 bgei r11, GT16 /* size is greater than 16MB */
186 bgei r11, GT8 /* size is greater than 8MB */
188 bgei r11, GT4 /* size is greater than 4MB */
189 /* size is less than 4MB */
191 bgei r11, GT2 /* size is greater than 2MB */
192 addik r9, r0, 0x0100000 /* TLB0 must be 1MB */
194 bgei r11, GT1 /* size is greater than 1MB */
198 ori r9, r0, 0x400000 /* TLB0 is 4MB */
200 GT16: /* TLB0 is 16MB */
[all …]
/openbmc/u-boot/cmd/
H A Dotp_info.h55 { 12, 2, 0, "VGA memory size : 8MB" },
56 { 12, 2, 1, "VGA memory size : 16MB" },
57 { 12, 2, 2, "VGA memory size : 32MB" },
58 { 12, 2, 3, "VGA memory size : 64MB" },
61 { 16, 1, 0, "Enable ARM JTAG debug" },
62 { 16, 1, 1, "Disable ARM JTAG debug" },
111 { 45, 3, 0, "Boot SPI flash size : 0MB" },
112 { 45, 3, 1, "Boot SPI flash size : 2MB" },
113 { 45, 3, 2, "Boot SPI flash size : 4MB" },
114 { 45, 3, 3, "Boot SPI flash size : 8MB" },
[all …]
/openbmc/linux/drivers/net/ethernet/apple/
H A Dmace.c73 * and another 16 bytes to allow us to align the dma command
74 * buffers on a 16 byte boundary.
307 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16); in dbdma_reset()
321 volatile struct mace __iomem *mb = mp->mace; in mace_reset() local
327 out_8(&mb->biucc, SWRST); in mace_reset()
328 if (in_8(&mb->biucc) & SWRST) { in mace_reset()
339 out_8(&mb->imr, 0xff); /* disable all intrs for now */ in mace_reset()
340 i = in_8(&mb->ir); in mace_reset()
341 out_8(&mb->maccc, 0); /* turn off tx, rx */ in mace_reset()
343 out_8(&mb->biucc, XMTSP_64); in mace_reset()
[all …]
/openbmc/linux/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
/openbmc/u-boot/doc/
H A DREADME.b4860qds65 - DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 4 GB
67 - DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB
69 - SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point 16x16 switch
79 - 16-bit NOR Flash / PROMJet
86 - JTAG/COP 16-pin header for any external TAP controller
172 0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
174 0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
176 0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
177 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
178 0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
[all …]
/openbmc/linux/Documentation/fb/
H A Dmatroxfb.rst51 16 0x111 0x182 0x114 0x18A
66 16 0x117 0x192 0x11A 0x19A 0x11E
94 architectures there are some glitches for 24bpp videomodes. 8, 16 and 32bpp
128 memory usable for on-screen display (i.e. max. 8 MB).
165 - 0 -> 2x128Kx32 chips, 2MB onboard, probably sgram
166 - 1 -> 2x128Kx32 chips, 4MB onboard, probably sgram
167 - 2 -> 2x256Kx32 chips, 4MB onboard, probably sgram
168 - 3 -> 2x256Kx32 chips, 8MB onboard, probably sgram
169 - 4 -> 2x512Kx16 chips, 8/16MB onboard, probably sdram only
171 - 6 -> 4x128Kx32 chips, 4MB onboard, probably sgram
[all …]
H A Dintel810.rst37 - Supports color depths of 8, 16, 24 and 32 bits per pixel
41 - Full and optimized hardware acceleration at 8, 16 and 24 bpp
88 select amount of system RAM in MB to allocate for the video memory
90 Recommendation: 1 - 4 MB.
123 select at what offset in MB of the logical memory to allocate the
126 offset (16 MB for a 64 MB aperture, 8 MB for a 32 MB aperture) will
127 avoid XFree86's usage and allows up to 7 MB/15 MB of framebuffer
129 (0 for maximum usage, 31/63 MB for the least amount). Note, an
133 (default = 8 or 16 MB)
195 will use 2 MB of System RAM. MTRR support will be enabled. The refresh rate
[all …]
/openbmc/u-boot/board/freescale/ls1043ardb/
H A DREADME24 - One 128MB NOR flash 16-bit data bus
25 - One 512 MB NAND flash with ECC support
30 - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
40 0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
41 0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
44 0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
45 0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
/openbmc/linux/arch/arc/plat-axs10x/
H A Daxs10x.c44 * | snps,dw-apb-intc (MB)| in axs10x_enable_gpio_intc_wire()
55 * DT hardware topology - connect MB intc directly to cpu intc in axs10x_enable_gpio_intc_wire()
94 char mb[32]; in axs10x_early_init() local
104 scnprintf(mb, 32, "MainBoard v%d", mb_rev); in axs10x_early_init()
105 axs10x_print_board_ver(CREG_MB_VER, mb); in axs10x_early_init()
121 * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
122 * of which maps to a corresponding 256MB aperture in Target slave memory map.
127 * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
131 * MB AXI Tunnel Master, which also has a mem map setup
133 * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
[all …]
/openbmc/linux/drivers/eisa/
H A Deisa.ids86 ALR3023 "ALR 16-bit VGA without Parallel port"
108 ARC0020 "Alta TokenCombo-16 S/U"
156 COG5000 "Cogent eMASTER+ AT Combo 16-Bit Workstation Ethernet Adapter"
246 CPQ5251 "Compaq 5/133 System Processor Board-2MB"
247 CPQ5253 "Compaq 5/166 System Processor Board-2MB"
248 CPQ5255 "Compaq 5/133 System Processor Board-1MB"
249 CPQ525D "Compaq 5/100 System Processor Board-1MB"
281 CPQ9018 "Compaq 486/33 Processor Board (8 MB)"
283 CPQ9035 "Compaq 486SX/16 Processor Board"
284 CPQ9036 "Compaq 486SX/25 Processor Board (8 MB)"
[all …]
/openbmc/linux/sound/isa/gus/
H A Dgus_io.c17 mb(); in snd_gf1_delay()
36 mb(); in __snd_gf1_ctrl_stop()
38 mb(); in __snd_gf1_ctrl_stop()
40 mb(); in __snd_gf1_ctrl_stop()
42 mb(); in __snd_gf1_ctrl_stop()
50 mb(); in __snd_gf1_write8()
52 mb(); in __snd_gf1_write8()
59 mb(); in __snd_gf1_look8()
67 mb(); in __snd_gf1_write16()
69 mb(); in __snd_gf1_write16()
[all …]
/openbmc/linux/arch/mips/include/asm/dec/
H A Dkn05.h7 * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
23 * The oncard MB (Memory Buffer) ASIC provides an additional address
24 * decoder. Certain address ranges within the "high" 16 slots are
34 #define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */
35 #define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */
36 #define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */
37 #define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */
48 * MB ASIC interrupt bits.
57 * Bits for the MB interrupt register.
64 * Bits for the MB control & status register.
[all …]
/openbmc/u-boot/arch/x86/cpu/quark/
H A Dmrc.c117 * 4Gbx16=15 4Gbx8=16 in mrc_adjust_params()
118 * 8Gbx16=16 8Gbx8=16 in mrc_adjust_params()
128 * (For 16 bit data bus, divide by 2) in mrc_adjust_params()
131 * 512Mb x16 0x008000000 ( 128MB) in mrc_adjust_params()
132 * 512Mb x8 0x010000000 ( 256MB) in mrc_adjust_params()
133 * 1Gb x16 0x010000000 ( 256MB) in mrc_adjust_params()
134 * 1Gb x8 0x020000000 ( 512MB) in mrc_adjust_params()
135 * 2Gb x16 0x020000000 ( 512MB) in mrc_adjust_params()
136 * 2Gb x8 0x040000000 (1024MB) in mrc_adjust_params()
137 * 4Gb x16 0x040000000 (1024MB) in mrc_adjust_params()
[all …]
/openbmc/u-boot/board/freescale/t208xqds/
H A DREADME13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
17 - 16 SerDes lanes up to 10.3125 GHz
42 SerDes lanes: 16 8
64 - 16 lanes up to 10.3125GHz
67 - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
69 - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
126 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
131 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
132 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
133 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
[all …]
/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_isr.c151 fctl = ~(abts->f_ctl[2] | 0x7F) << 16 | in qla24xx_process_abts()
155 abts_rsp->f_ctl[2] = fctl >> 16 & 0xff; in qla24xx_process_abts()
349 uint16_t mb[8]; in qla2100_intr_handler() local
393 mb[0] = RD_MAILBOX_REG(ha, reg, 0); in qla2100_intr_handler()
394 if (mb[0] > 0x3fff && mb[0] < 0x8000) { in qla2100_intr_handler()
395 qla2x00_mbx_completion(vha, mb[0]); in qla2100_intr_handler()
397 } else if (mb[0] > 0x7fff && mb[0] < 0xc000) { in qla2100_intr_handler()
398 mb[1] = RD_MAILBOX_REG(ha, reg, 1); in qla2100_intr_handler()
399 mb[2] = RD_MAILBOX_REG(ha, reg, 2); in qla2100_intr_handler()
400 mb[3] = RD_MAILBOX_REG(ha, reg, 3); in qla2100_intr_handler()
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2-xmc.dts83 nand-bus-width = <16>;
84 brcm,nand-oob-sector-size = <16>;
90 reg = <0x00000000 0x00280000>; /* 2.5MB */
96 reg = <0x00280000 0x00040000>; /* 0.25MB */
102 reg = <0x002c0000 0x00040000>; /* 0.25MB */
108 reg = <0x00300000 0x03d00000>; /* 61MB */
114 reg = <0x04000000 0x06400000>; /* 100MB */
119 reg = <0x0a400000 0x35c00000>; /* 860MB */
179 reg = <0x00200000 0x00e00000>; /* 14MB */
184 reg = <0x01000000 0x01000000>; /* 16MB */
/openbmc/u-boot/board/freescale/ls2080aqds/
H A DREADME16 - SERDES Connections, 16 lanes supporting:
30 - One in-socket 128 MB NOR flash 16-bit data bus
31 - One 512 MB NAND flash with ECC support
46 - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
47 - 8 MB high-speed flash Memory (up to 104 MHz)
48 - 512 MB low-speed flash Memory (up to 40 MHz)
73 0x30000000 - 0x37ffffff : 128MB : NOR flash
74 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
75 0x3C000000 - 0x40000000 : 64MB : FPGA etc
79 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
[all …]

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