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/openbmc/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu2_hw_h264_dec.c28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
[all …]
/openbmc/linux/lib/crypto/
H A Dblake2s-generic.c20 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
21 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
22 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
23 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
24 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
25 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
26 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
27 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
28 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
29 { 10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0 },
[all …]
/openbmc/linux/crypto/
H A Dblake2b_generic.c26 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
27 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
28 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
29 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
30 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
31 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
32 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
33 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
34 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
35 { 10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0 },
[all …]
/openbmc/linux/arch/arm/crypto/
H A Dblake2s-core.S113 // Execute one round of BLAKE2s by updating the state matrix v[0..15]. v[0..9]
115 // spilling v[8..9], then to v[9..15], then to the message block. r10-r12 and
132 // (v[0], v[4], v[8], v[12]) and (v[1], v[5], v[9], v[13]).
133 __ldrd r10, r11, sp, 16 // load v[12] and v[13]
140 // (v[2], v[6], v[10], v[14]) and (v[3], v[7], v[11], v[15]).
141 __ldrd r8, r9, sp, 8 // load v[10] and v[11]
142 __ldrd r10, r11, sp, 24 // load v[14] and v[15]
145 str r10, [sp, #24] // store v[14]
146 // v[10], v[11], and v[15] are used below, so no need to store them yet.
152 // (v[0], v[5], v[10], v[15]) and (v[1], v[6], v[11], v[12]).
[all …]
H A Dblake2b-neon-core.S63 // Execute one round of BLAKE2b by updating the state matrix v[0..15] in the
73 // (v[0], v[4], v[8], v[12]), (v[1], v[5], v[9], v[13]),
74 // (v[2], v[6], v[10], v[14]), and (v[3], v[7], v[11], v[15]).
145 // (v[0], v[5], v[10], v[15]), (v[1], v[6], v[11], v[12]),
146 // (v[2], v[7], v[8], v[13]), and (v[3], v[4], v[9], v[14]).
274 // 'v'. Fortunately, there are exactly enough NEON registers to fit the
275 // entire state matrix in q0-q7 and the entire message block in q8-15.
285 veor q6, q6, q14 // v[12..13] = IV[4..5] ^ t[0..1]
287 veor q7, q7, q15 // v[14..15] = IV[6..7] ^ f[0..1]
295 _blake2b_round 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
[all …]
/openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/fonts/
H A Dglyphicons-halflings-regular.svg12 …v-224l158 158q7 7 18 8t19 -6l106 -106q7 -8 6 -19t-8 -18l-158 -158h224q10 0 18.5 -7.5t10.5 -17.5q6 …
13 …50 1100h200q21 0 35.5 -14.5t14.5 -35.5v-350h350q21 0 35.5 -14.5t14.5 -35.5v-200q0 -21 -14.5 -35.5t…
15 …6t-3 -14l-120 -160q-6 -8 -18 -14t-22 -6h-125v-100h275q10 0 13 -6t-3 -14l-120 -160q-6 -8 -18 -14t-2…
30 …v-16.5v-16.5q0 -36 -0.5 -57t-6.5 -61t-17 -65t-35 -57t-57 -50.5t-86 -31.5t-120 -13h-178l-2 -100h288…
31 <glyph unicode="&#x2212;" d="M250 700h800q21 0 35.5 -14.5t14.5 -35.5v-200q0 -21 -14.5 -35.5t-35.5 -…
32 …v-150q0 -21 -14.5 -35.5t-35.5 -14.5h-50v-100q0 -91 -49.5 -165.5t-130.5 -109.5q81 -35 130.5 -109.5t…
35 …v-42h-1200v42q0 21 15 39.5t35 18.5h30l468 746l-135 183q-10 16 -5.5 34t20.5 28t34 5.5t28 -20.5l111 …
36 …-13 -5.5t-5 12.5v550q0 10 5 12.5t13 -5.5zM918 618l264 264q8 8 13 5.5t5 -12.5v-550q0 -10 -5 -12.5t-…
38 <glyph unicode="&#xe001;" d="M700 650v-550h250q21 0 35.5 -14.5t14.5 -35.5v-50h-800v50q0 21 14.5 35.…
39 …017l645 163q39 15 63 0t24 -49v-831q0 -55 -41.5 -95.5t-111.5 -63.5q-79 -25 -147 -4.5t-86 75t25.5 11…
[all …]
/openbmc/linux/drivers/gpu/drm/exynos/
H A Dregs-scaler.h56 * 1 70 74 78 7c 150 154 158 15c
158 #define SCALER_INT_EN_ILLEGAL_DST_CB_BASE (1 << 15)
186 #define SCALER_INT_STATUS_ILLEGAL_DST_CB_BASE (1 << 15)
206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
222 #define SCALER_L8 15
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
234 #define SCALER_SRC_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0) argument
238 #define SCALER_SRC_Y_POS_SET_YH_POS(v) SCALER_SET(v, 31, 16) argument
239 #define SCALER_SRC_Y_POS_GET_YV_POS(r) SCALER_GET(r, 15, 0)
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Datafb_iplan2p8.c53 if (!((sx ^ dx) & 15)) { in atafb_iplan2p8_copyarea()
57 src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
58 dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
59 if (sx & 15) { in atafb_iplan2p8_copyarea()
78 if (width & 15) in atafb_iplan2p8_copyarea()
82 src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
83 dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
85 if ((sx + width) & 15) { in atafb_iplan2p8_copyarea()
104 if (sx & 15) in atafb_iplan2p8_copyarea()
113 u32 pval[4], v, v1, mask; in atafb_iplan2p8_copyarea() local
[all …]
H A Datafb_iplan2p4.c46 if (!((sx ^ dx) & 15)) { in atafb_iplan2p4_copyarea()
50 src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL); in atafb_iplan2p4_copyarea()
51 dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL); in atafb_iplan2p4_copyarea()
52 if (sx & 15) { in atafb_iplan2p4_copyarea()
71 if (width & 15) in atafb_iplan2p4_copyarea()
75 src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p4_copyarea()
76 dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p4_copyarea()
78 if ((sx + width) & 15) { in atafb_iplan2p4_copyarea()
97 if (sx & 15) in atafb_iplan2p4_copyarea()
106 u32 pval[4], v, v1, mask; in atafb_iplan2p4_copyarea() local
[all …]
H A Dvalkyriefb.h8 * Vmode-switching changes and vmode 15/17 modifications created 29 August
101 15,
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
107 /* Register values for 1024x768, 72Hz mode (15) */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
110 * caused the 15" Apple Studio Display to not work in this mode. While this
117 15,
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
119 /* I interpolated the V=69.71 from the vmode 14 and old 15
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
[all …]
H A Datafb_iplan2p2.c46 if (!((sx ^ dx) & 15)) { in atafb_iplan2p2_copyarea()
50 src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL); in atafb_iplan2p2_copyarea()
51 dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL); in atafb_iplan2p2_copyarea()
52 if (sx & 15) { in atafb_iplan2p2_copyarea()
71 if (width & 15) in atafb_iplan2p2_copyarea()
75 src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p2_copyarea()
76 dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p2_copyarea()
78 if ((sx + width) & 15) { in atafb_iplan2p2_copyarea()
97 if (sx & 15) in atafb_iplan2p2_copyarea()
106 u32 pval[4], v, v1, mask; in atafb_iplan2p2_copyarea() local
[all …]
/openbmc/linux/arch/arm64/crypto/
H A Dsha512-ce-core.S15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
90 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
91 add v\i3\().2d, v\i3\().2d, v5.2d
93 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
94 sha512su0 v\in0\().2d, v\in1\().2d
98 sha512su1 v\in0\().2d, v\in2\().2d, v5.2d
100 add v\i4\().2d, v\i1\().2d, v\i3\().2d
[all …]
/openbmc/openbmc-test-automation/docs/
H A Dcode_update.md20 …$ robot -v OPENBMC_HOST:x.x.x.x -v IMAGE_FILE_PATH:<image path>/obmc-phosphor-image-witherspoon.ub…
25 …$ robot -v OPENBMC_HOST:x.x.x.x -v IMAGE_FILE_PATH:<image path>/obmc-phosphor-image-witherspoon.ub…
37 …$ robot -v OPENBMC_HOST:x.x.x.x -v IMAGE_FILE_PATH:<image path>/witherspoon.pnor.squashfs.tar --in…
42 …$ robot -v OPENBMC_HOST:x.x.x.x -v IMAGE_FILE_PATH:<image path>/witherspoon.pnor.squashfs.tar --in…
60 …$ robot -v OPENBMC_HOST:x.x.x.x -v IMAGE_FILE_PATH:<image path>/obmc-phosphor-image-witherspoon.ub…
70 …$ robot -v OPENBMC_HOST:x.x.x.x -v IMAGE_FILE_PATH:<image path>/witherspoon.pnor.squashfs.tar --in…
82 …$ robot -v OPENBMC_HOST:x.x.x.x -v FILE_PATH:<image path>/zaius-<date time>.all.tar --include Init…
92 $ robot -v OPENBMC_HOST:x.x.x.x -v PNOR_IMAGE_PATH:<image path>/zaius.pnor test_bios_update.robot
106 -rw-r--r-- jenkins-op/jenkins-op 306804 2021-05-15 22:00 image-u-boot
108 -rw-r--r-- jenkins-op/jenkins-op 19861504 2021-05-15 22:00 image-rofs
[all …]
/openbmc/linux/drivers/net/ethernet/altera/
H A Daltera_msgdmahw.h19 * bit 15:0 sequence number
22 * bit 15:0 read stride
39 #define MSGDMA_DESC_CTL_EARLY_IRQ BIT(15)
81 * bit 15:0 - read fill level
83 u32 resp_fill_level; /* bit 15:0 */
85 * bit 15:0 - read sequence number
105 #define MSGDMA_CSR_STAT_BUSY_GET(v) GET_BIT_VALUE(v, 0) argument
106 #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 1) argument
107 #define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v) GET_BIT_VALUE(v, 2) argument
108 #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 3) argument
[all …]
/openbmc/linux/arch/alpha/kernel/
H A Dentry.S41 * regs 9-15 preserved by C code
157 .cfi_rel_offset $15, 48
168 .cfi_restore $15
196 /* save $9 - $15 so the inline exception code can manipulate them. */
205 stq $15, 48($sp)
212 .cfi_rel_offset $15, 48
225 ldq $15, 48($sp)
233 .cfi_restore $15
271 stq $15, 120($sp)
299 .cfi_rel_offset $15, 15*8
[all …]
/openbmc/phosphor-host-ipmid/test/message/
H A Dpack.cpp26 uint8_t v = 4; in TEST() local
27 p.pack(v); in TEST()
29 ASSERT_EQ(p.size(), sizeof(v)); in TEST()
38 uint16_t v = 0x8604; in TEST() local
39 p.pack(v); in TEST()
41 ASSERT_EQ(p.size(), sizeof(v)); in TEST()
50 uint32_t v = 0x02008604; in TEST() local
51 p.pack(v); in TEST()
53 ASSERT_EQ(p.size(), sizeof(v)); in TEST()
62 uint64_t v = 0x1122334402008604ull; in TEST() local
[all …]
H A Dunpack.cpp25 uint8_t v; in TEST() local
27 ASSERT_EQ(p.unpack(v), 0); in TEST()
32 ASSERT_EQ(v, k); in TEST()
39 uint8_t v; in TEST() local
41 ASSERT_EQ(p.unpack(v), 0); in TEST()
46 ASSERT_EQ(v, k); in TEST()
53 uint8_t v = 0; in TEST() local
55 ASSERT_NE(p.unpack(v), 0); in TEST()
58 // check that v is zero in TEST()
59 ASSERT_EQ(v, 0); in TEST()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dmem.h57 #define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */ argument
58 #define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */ argument
59 #define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */ argument
60 #define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */ argument
61 #define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */ argument
62 #define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */ argument
63 #define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */ argument
64 #define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */ argument
77 #define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */ argument
78 #define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */ argument
[all …]
/openbmc/linux/drivers/staging/media/sunxi/cedrus/
H A Dcedrus_regs.h13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
64 #define VE_PRIMARY_FB_LINE_STRIDE_LUMA(s) SHIFT_AND_MASK_BITS(s, 15, 0)
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
107 ((v) ? BIT(6) : 0)
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
109 ((v) ? BIT(5) : 0)
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
[all …]
/openbmc/linux/arch/x86/include/asm/
H A Dperf_event_p4.h40 #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) argument
41 #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) argument
42 #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) argument
62 #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) argument
63 #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT) argument
81 #define p4_config_pack_escr(v) (((u64)(v)) << 32) argument
82 #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) argument
83 #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) argument
84 #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) argument
86 #define p4_config_unpack_emask(v) \ argument
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dadi,max98396.yaml13 The MAX98396 is a mono Class-DG speaker amplifier with I/V sense.
28 description: A 1.8V supply that powers up the AVDD pin.
31 description: A 1.2V supply that powers up the DVDD pin.
34 description: A 1.2V or 1.8V supply that powers up the VDDIO pin.
37 description: A 3.0V to 20V supply that powers up the PVDD pin.
40 description: A 3.3V to 5.5V supply that powers up the VBAT pin.
46 maximum: 15
53 maximum: 15
60 maximum: 15
69 maximum: 15
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/qca953x/
H A Dlowlevel_init.S23 ((0x3 & (ahbdiv - 1)) << 15) )
25 #define SET_FIELD(name, v) (((v) & QCA953X_##name##_MASK) << \ argument
28 #define DPLL2_KI(v) SET_FIELD(SRIF_DPLL2_KI, v) argument
29 #define DPLL2_KD(v) SET_FIELD(SRIF_DPLL2_KD, v) argument
33 #define PLL_CPU_NFRAC(v) SET_FIELD(PLL_CPU_CONFIG_NFRAC, v) argument
34 #define PLL_CPU_NINT(v) SET_FIELD(PLL_CPU_CONFIG_NINT, v) argument
35 #define PLL_CPU_REFDIV(v) SET_FIELD(PLL_CPU_CONFIG_REFDIV, v) argument
36 #define PLL_CPU_OUTDIV(v) SET_FIELD(PLL_CPU_CONFIG_OUTDIV, v) argument
43 #define PLL_DDR_NFRAC(v) SET_FIELD(PLL_DDR_CONFIG_NFRAC, v) argument
44 #define PLL_DDR_NINT(v) SET_FIELD(PLL_DDR_CONFIG_NINT, v) argument
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dcrm_regs.h225 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
411 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) argument
414 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) argument
415 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
416 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
417 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) argument
421 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) argument
424 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) argument
426 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15)
427 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15
[all …]
/openbmc/linux/sound/ppc/
H A Dsnd_ps3_reg.h72 31 24 23 16 15 8 7 0
95 31 24 23 16 15 8 7 0
105 31 24 23 16 15 8 7 0
124 31 24 23 16 15 8 7 0
149 #define PS3_AUDIO_AX_MCTRL_AAOMT (1 << 15) /* RWIVF */
154 31 24 23 16 15 8 7 0
184 31 24 23 16 15 8 7 0
224 31 24 23 16 15 8 7 0
235 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY1 (0x0 << 12) /* RWI-V */
236 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY2 (0x1 << 12) /* RW--V */
[all …]
/openbmc/linux/lib/
H A Dbitfield_kunit.c11 #define CHECK_ENC_GET_U(tp, v, field, res) do { \ argument
15 _res = u##tp##_encode_bits(v, field); \
17 "u" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != " #res "\n", \
20 u##tp##_get_bits(_res, field) != v); \
24 #define CHECK_ENC_GET_LE(tp, v, field, res) do { \ argument
28 _res = le##tp##_encode_bits(v, field); \
31 "le" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx",\
35 le##tp##_get_bits(_res, field) != v);\
39 #define CHECK_ENC_GET_BE(tp, v, field, res) do { \ argument
43 _res = be##tp##_encode_bits(v, field); \
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