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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmicrochip,sparx5-serdes.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
21 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
22 * Adjustable tx de-emphasis (FFE)
31 The SERDES6G is a high-speed SERDES interface, which can operate at
34 * 100 Mbps (100BASE-FX)
35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
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H A Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
21 'tx-p2p-microvolt-names' property must be provided and contain
24 tx-p2p-microvolt-names:
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/openbmc/u-boot/include/linux/
H A Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
24 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
37 #define MDIO_CTRL2 7 /* 10G control 2 */
38 #define MDIO_STAT2 8 /* 10G status 2 */
39 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
40 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
41 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
52 /* Media-dependent registers. */
53 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
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/openbmc/linux/include/uapi/linux/
H A Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
38 #define MDIO_CTRL2 7 /* 10G control 2 */
39 #define MDIO_STAT2 8 /* 10G status 2 */
40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
58 /* Media-dependent registers. */
59 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
20 local-mac-address:
23 $ref: /schemas/types.yaml#/definitions/uint8-array
27 mac-address:
32 local-mac-address property.
33 $ref: /schemas/types.yaml#/definitions/uint8-array
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H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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H A Dsff,sfp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
11 - Russell King <linux@armlinux.org.uk>
16 - sff,sfp # for SFP modules
17 - sff,sff # for soldered down SFF modules
19 i2c-bus:
24 maximum-power-milliwatt:
29 allowable by a module in the slot, in milli-Watts. Presently, modules can
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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-class-net-phydev24 This attribute contains the 32-bit PHY Identifier as reported
41 <empty> (not available), mii, gmii, sgmii, tbi, rev-mii,
42 rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii
43 xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui,
44 xaui, 10gbase-kr, unknown
60 32-bit hexadecimal number representing a bit mask of the
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
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/openbmc/linux/drivers/net/phy/
H A Dmarvell10g.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 10G 88x3310 PHY driver
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
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H A Dphylink.c1 // SPDX-License-Identifier: GPL-2.0
4 * technologies such as SFP cages where the PHY is hot-pluggable.
44 * struct phylink - internal data type for phylink
60 u8 link_port; /* The current non-phy ethtool port */
93 if ((pl)->config->type == PHYLINK_NETDEV) \
94 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \
95 else if ((pl)->config->type == PHYLINK_DEV) \
96 dev_printk(level, (pl)->dev, fmt, ##__VA_ARGS__); \
108 if ((pl)->config->type == PHYLINK_NETDEV) \
109 netdev_dbg((pl)->netdev, fmt, ##__VA_ARGS__); \
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/openbmc/linux/include/linux/
H A Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2006-2009 Solarflare Communications Inc.
38 /* Bus address of the MDIO device (0-31) */
71 * up device-specific structures, if any
92 dev_set_drvdata(&mdio->dev, data); in mdiodev_set_drvdata()
97 return dev_get_drvdata(&mdio->dev); in mdiodev_get_drvdata()
111 get_device(&mdiodev->dev); in mdio_device_get()
135 * struct mdio_if_info - Ethernet controller MDIO interface
138 * non-zero unless @prtad = %MDIO_PRTAD_NONE.
160 #define MDIO_PRTAD_NONE (-1)
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H A Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
79 * Set phydev->irq to PHY_POLL if interrupts are not supported,
83 #define PHY_POLL -1
84 #define PHY_MAC_INTERRUPT -2
93 * enum phy_interface_t - Interface Mode definitions
95 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch
97 * @PHY_INTERFACE_MODE_MII: Media-independent interface
98 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface
99 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface
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/openbmc/u-boot/board/freescale/t4qds/
H A DREADME2 --------
3 The T4240QDS is a high-performance computing evaluation, development and test
5 optimized to support the high-bandwidth DDR3 memory ports, as well as the
6 highly-configurable SerDes ports. The system is lead-free and RoHS-compliant.
10 32 lanes grouped into four 8-lane banks
12 - High-speed crosspoint switch fabric on selected lanes
13 - Two PCI Express slots with side-band connector supporting
14 - SGMII
15 - XAUI
16 - HiGig
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H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
111 struct t4240qds_mdio *priv = bus->priv; in t4240qds_mdio_read()
113 t4240qds_mux_mdio(priv->muxval); in t4240qds_mdio_read()
115 return priv->realbus->read(priv->realbus, addr, devad, regnum); in t4240qds_mdio_read()
121 struct t4240qds_mdio *priv = bus->priv; in t4240qds_mdio_write()
123 t4240qds_mux_mdio(priv->muxval); in t4240qds_mdio_write()
125 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); in t4240qds_mdio_write()
130 struct t4240qds_mdio *priv = bus->priv; in t4240qds_mdio_reset()
132 return priv->realbus->reset(priv->realbus); in t4240qds_mdio_reset()
142 return -1; in t4240qds_mdio_init()
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/openbmc/u-boot/board/freescale/ls1046aqds/
H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
92 struct ls1046aqds_mdio *priv = bus->priv; in ls1046aqds_mdio_read()
94 ls1046aqds_mux_mdio(priv->muxval); in ls1046aqds_mdio_read()
96 return priv->realbus->read(priv->realbus, addr, devad, regnum); in ls1046aqds_mdio_read()
102 struct ls1046aqds_mdio *priv = bus->priv; in ls1046aqds_mdio_write()
104 ls1046aqds_mux_mdio(priv->muxval); in ls1046aqds_mdio_write()
106 return priv->realbus->write(priv->realbus, addr, devad, in ls1046aqds_mdio_write()
112 struct ls1046aqds_mdio *priv = bus->priv; in ls1046aqds_mdio_reset()
114 return priv->realbus->reset(priv->realbus); in ls1046aqds_mdio_reset()
124 return -1; in ls1046aqds_mdio_init()
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/openbmc/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v2.c2 * AMD 10Gb Ethernet driver
125 #include "xgbe-common.h"
149 /* Rate-change complete wait/retry count */
152 /* CDR delay values for KR support (in usec) */
158 #define XGBE_RRC_FREQUENCY 10
276 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
277 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
284 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
285 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
306 /* Re-driver related definitions */
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/openbmc/u-boot/board/freescale/t208xqds/
H A DREADME1 The T2080QDS is a high-performance computing evaluation, development and
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
[all …]
H A Deth_t208xqds.c1 // SPDX-License-Identifier: GPL-2.0+
134 struct t208xqds_mdio *priv = bus->priv; in t208xqds_mdio_read()
136 t208xqds_mux_mdio(priv->muxval); in t208xqds_mdio_read()
138 return priv->realbus->read(priv->realbus, addr, devad, regnum); in t208xqds_mdio_read()
144 struct t208xqds_mdio *priv = bus->priv; in t208xqds_mdio_write()
146 t208xqds_mux_mdio(priv->muxval); in t208xqds_mdio_write()
148 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); in t208xqds_mdio_write()
153 struct t208xqds_mdio *priv = bus->priv; in t208xqds_mdio_reset()
155 return priv->realbus->reset(priv->realbus); in t208xqds_mdio_reset()
165 return -1; in t208xqds_mdio_init()
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/openbmc/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_82599.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
65 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_mac_link_ops_82599()
70 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && in ixgbe_init_mac_link_ops_82599()
72 mac->ops.disable_tx_laser = in ixgbe_init_mac_link_ops_82599()
74 mac->ops.enable_tx_laser = in ixgbe_init_mac_link_ops_82599()
76 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; in ixgbe_init_mac_link_ops_82599()
78 mac->ops.disable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
79 mac->ops.enable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
80 mac->ops.flap_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
[all …]
/openbmc/linux/drivers/net/ethernet/freescale/fman/
H A Dfman_memac.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
14 #include <linux/pcs-lynx.h>
56 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
57 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */
58 #define IF_MODE_MII 0x00000001 /* 30-31 MII interface */
59 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
62 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
63 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
64 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */
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/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.c1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
257 /* NOTE: must be first condition checked - in bnx2x_check_lfa()
262 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
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H A Dbnx2x_hsi.h3 * Copyright (c) 2007-2013 Broadcom Corporation
125 /* Up to 16 bytes of NULL-terminated string */
145 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
150 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
151 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
153 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
154 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
156 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
157 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
409 /* Default values: 2P-64, 4P-32 */
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/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_main.c1 // SPDX-License-Identifier: GPL-2.0
76 writel(data, priv->swth_base[0] + offset); in mvpp2_write()
81 return readl(priv->swth_base[0] + offset); in mvpp2_read()
86 return readl_relaxed(priv->swth_base[0] + offset); in mvpp2_read_relaxed()
91 return cpu % priv->nthreads; in mvpp2_cpu_to_thread()
96 writel(data, priv->cm3_base + offset); in mvpp2_cm3_write()
101 return readl(priv->cm3_base + offset); in mvpp2_cm3_read()
124 * - per-thread registers, where each thread has its own copy of the
140 * - global registers that must be accessed through a specific thread
141 * window, because they are related to an access to a per-thread
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