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/openbmc/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
12 # 8, 16, 32 register bits (default is 8)
13 # v1.1 defined in version 1.1
19 module_model_id 0x0000 16
[all …]
/openbmc/linux/arch/arm64/crypto/
H A Dsm4-ce-gcm-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SM4-GCM AEAD Algorithm using ARMv8 Crypto Extensions
14 #include "sm4-ce-asm.h"
16 .arch armv8-a+crypto
18 .irp b, 0, 1, 2, 3, 24, 25, 26, 27, 28, 29, 30, 31
37 * output: r0:r1 (low 128-bits in r0, high in r1)
40 ext T0.16b, m1.16b, m1.16b, #8; \
41 pmull r0.1q, m0.1d, m1.1d; \
42 pmull T1.1q, m0.1d, T0.1d; \
43 pmull2 T0.1q, m0.2d, T0.2d; \
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H A Dghash-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 - 2018 Linaro Ltd. <ard.biesheuvel@linaro.org>
61 .arch armv8-a+crypto
64 pmull \rd\().1q, \rn\().1d, \rm\().1d
68 pmull2 \rd\().1q, \rn\().2d, \rm\().2d
72 ext t3.8b, \ad\().8b, \ad\().8b, #1 // A1
80 tbl t3.16b, {\ad\().16b}, perm1.16b // A1
81 tbl t5.16b, {\ad\().16b}, perm2.16b // A2
82 tbl t7.16b, {\ad\().16b}, perm3.16b // A3
96 __pmull_p8_tail \rq, \ad\().16b, SHASH.16b, 16b, 2, sh1, sh2, sh3, sh4
[all …]
H A Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
17 .set .Lv\b\().16b, \b
24 .inst 0xce000000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
28 .inst 0xce608c00 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
32 .inst 0xce200000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
36 .inst 0xce800000 | .L\rd | (.L\rn << 5) | ((\imm6) << 10) | (.L\rm << 16)
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
[all …]
H A Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aesce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
12 .arch armv8-a+crypto
19 ld1 {v0.16b}, [x0] /* load mac */
20 cbz w3, 1f
21 sub w3, w3, #16
22 eor v1.16b, v1.16b, v1.16b
23 0: ldrb w7, [x1], #1 /* get 1 byte of input */
24 subs w2, w2, #1
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H A Dpolyval-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
10 * ..., h^1 in the POLYVAL finite field. This precomputation allows us to split
14 * than 128. We then compute p(x) = h^8m_0 + ... + h^1m_7 where multiplication
18 * modulus g(x) = x^128 + x^127 + x^126 + x^121 + 1.
20 * This two step process is equivalent to computing h^8m_0 + ... + h^1m_7 where
22 * two-step process only requires 1 finite field reduction for every 8
65 .arch armv8-a+crypto
72 * Computes the product of two 128-bit polynomials in X and Y and XORs the
73 * components of the 256-bit product into LO, MI, HI.
84 * Later, the 256-bit result can be extracted as:
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H A Dsm4-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SM4-CCM AEAD Algorithm using ARMv8 Crypto Extensions
13 #include "sm4-ce-asm.h"
15 .arch armv8-a+crypto
17 .irp b, 0, 1, 8, 9, 10, 11, 12, 13, 14, 15, 16, 24, 25, 26, 27, 28, 29, 30, 31
32 mov vctr.d[1], x8; \
34 adds x8, x8, #1; \
35 rev64 vctr.16b, vctr.16b; \
49 ld1 {RMAC.16b}, [x1]
57 ld1 {v0.16b-v3.16b}, [x2], #64
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H A Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
21 .inst 0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
25 .inst 0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
33 .inst 0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
37 * The SHA-512 round constants
85 ld1 {v\rc1\().2d}, [x4], #16
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
89 ext v5.16b, v5.16b, v5.16b, #8
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/openbmc/linux/arch/alpha/kernel/
H A Dsys_takara.c1 // SPDX-License-Identifier: GPL-2.0
34 static unsigned long cached_irq_mask[2] = { -1, -1 };
41 mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30)); in takara_update_irq_hw()
42 regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c); in takara_update_irq_hw()
49 unsigned int irq = d->irq; in takara_enable_irq()
51 mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63))); in takara_enable_irq()
58 unsigned int irq = d->irq; in takara_disable_irq()
60 mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63)); in takara_disable_irq()
99 if (intstatus & 8) handle_irq(16+3); in takara_device_interrupt()
100 if (intstatus & 4) handle_irq(16+2); in takara_device_interrupt()
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H A Dsys_rx164.c1 // SPDX-License-Identifier: GPL-2.0
51 rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); in rx164_enable_irq()
57 rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); in rx164_disable_irq()
85 pld &= pld - 1; /* clear least bit set */ in rx164_device_interrupt()
89 handle_irq(16+i); in rx164_device_interrupt()
100 for (i = 16; i < 40; ++i) { in rx164_init_irq()
108 if (request_irq(16 + 20, no_action, 0, "isa-cascade", NULL)) in rx164_init_irq()
109 pr_err("Failed to register isa-cascade interrupt\n"); in rx164_init_irq()
120 * 1 7 4 9 14 19
123 * 4 10 1 6 11 16
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H A Dsys_miata.c1 // SPDX-License-Identifier: GPL-2.0
39 irq = (vector - 0x800) >> 4; in miata_srm_device_interrupt()
47 * for reporting any interrupts (the PCI-ISA bridge, bit 7, isn't in miata_srm_device_interrupt()
49 * vectors 0x800-0x8f0). in miata_srm_device_interrupt()
53 * So, here's this grotty hack... :-( in miata_srm_device_interrupt()
55 if (irq >= 16) in miata_srm_device_interrupt()
76 NMI (1), or EIDE (9). in miata_init_irq()
83 if (request_irq(16 + 2, no_action, 0, "halt-switch", NULL)) in miata_init_irq()
84 pr_err("Failed to register halt-switch interrupt\n"); in miata_init_irq()
85 if (request_irq(16 + 6, no_action, 0, "timer-cascade", NULL)) in miata_init_irq()
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H A Dsys_noritake.c1 // SPDX-License-Identifier: GPL-2.0
44 mask >>= 16; in noritake_update_irq_hw()
53 noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16)); in noritake_enable_irq()
59 noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16))); in noritake_disable_irq()
77 | ((unsigned long) inw(0x54a) << 16) in noritake_device_interrupt()
87 pld &= pld - 1; /* clear least bit set */ in noritake_device_interrupt()
88 if (i < 16) { in noritake_device_interrupt()
101 irq = (vector - 0x800) >> 4; in noritake_srm_device_interrupt()
110 * So, here's this additional grotty hack... :-( in noritake_srm_device_interrupt()
112 if (irq >= 16) in noritake_srm_device_interrupt()
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H A Dsys_dp264.c1 // SPDX-License-Identifier: GPL-2.0
50 unsigned long isa_enable = 1UL << 55; in tsunami_update_irq_hw()
59 mask1 = mask & cpu_irq_affinity[1]; in tsunami_update_irq_hw()
64 else if (bcpu == 1) mask1 |= isa_enable; in tsunami_update_irq_hw()
68 dim0 = &cchip->dim0.csr; in tsunami_update_irq_hw()
69 dim1 = &cchip->dim1.csr; in tsunami_update_irq_hw()
70 dim2 = &cchip->dim2.csr; in tsunami_update_irq_hw()
71 dim3 = &cchip->dim3.csr; in tsunami_update_irq_hw()
73 if (!cpu_possible(1)) dim1 = &dummy; in tsunami_update_irq_hw()
88 if (bcpu == 0) dimB = &cchip->dim0.csr; in tsunami_update_irq_hw()
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H A Dsys_cabriolet.c1 // SPDX-License-Identifier: GPL-2.0
43 int ofs = (irq - 16) / 8; in cabriolet_update_irq_hw()
44 outb(mask >> (16 + ofs * 8), 0x804 + ofs); in cabriolet_update_irq_hw()
50 cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq)); in cabriolet_enable_irq()
56 cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq); in cabriolet_disable_irq()
73 pld = inb(0x804) | (inb(0x805) << 8) | (inb(0x806) << 16); in cabriolet_device_interrupt()
81 pld &= pld - 1; /* clear least bit set */ in cabriolet_device_interrupt()
85 handle_irq(16 + i); in cabriolet_device_interrupt()
106 for (i = 16; i < 35; ++i) { in common_init_irq()
114 if (request_irq(16 + 4, no_action, 0, "isa-cascade", NULL)) in common_init_irq()
[all …]
/openbmc/linux/arch/powerpc/crypto/
H A Daes-gcm-p10.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 # Accelerated AES-GCM stitched implementation for ppc64le.
5 # Copyright 2022- IBM Inc. All rights reserved
22 # Hash keys = v3 - v14
29 # v31 - counter 1
32 # vs0 - vs14 for round keys
35 # This implementation uses stitched AES-GCM approach to improve overall performance.
48 # v15 - v18 - input states
49 # vs1 - vs9 - round keys
52 xxlor 19+32, 1, 1
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H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
14 # 1. a += b; d ^= a; d <<<= 16;
19 # row1 = (row1 + row2), row4 = row1 xor row4, row4 rotate each word by 16
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
55 li 16, \OFFSET
56 stvx \VRS, 16, \FRAME
60 li 16, \OFFSET
61 stxvx \VSX, 16, \FRAME
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/openbmc/linux/arch/alpha/lib/
H A Dev6-memcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memcpy.S
4 * 21264 version by Rick Gorton <rick.gorton@alpha-processor.com>
8 * - memory accessed as aligned quadwords only
9 * - uses bcmpge to compare 8 bytes in parallel
14 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
16 * E - either cluster
17 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
18 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
21 * $1,$2, - scratch
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H A Dev6-copy_page.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-copy_page.S
13 -----------------------------
28 9 cycles but I was not able to get it to run that fast -- the initial
34 -------------------------------------
45 --------------------------------------
51 forced me to add another cycle to the inner-most kernel - up to 11
68 /* Prefetch 5 read cachelines; write-hint 10 cache lines. */
69 wh64 ($16)
72 lda $1,1*64($16)
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/openbmc/linux/drivers/gpu/drm/tests/
H A Ddrm_rect_test.c1 // SPDX-License-Identifier: GPL-2.0
19 KUNIT_EXPECT_EQ(test, r->x1, expected->x1); in drm_rect_compare()
20 KUNIT_EXPECT_EQ(test, r->y1, expected->y1); in drm_rect_compare()
36 drm_rect_init(&clip, 1, 1, 1, 1); in drm_test_rect_clip_scaled_div_by_zero()
44 drm_rect_init(&clip, 1, 1, 1, 1); in drm_test_rect_clip_scaled_div_by_zero()
56 /* 1:1 scaling */ in drm_test_rect_clip_scaled_not_clipped()
57 drm_rect_init(&src, 0, 0, 1 << 16, 1 << 16); in drm_test_rect_clip_scaled_not_clipped()
58 drm_rect_init(&dst, 0, 0, 1, 1); in drm_test_rect_clip_scaled_not_clipped()
59 drm_rect_init(&clip, 0, 0, 1, 1); in drm_test_rect_clip_scaled_not_clipped()
63 KUNIT_EXPECT_FALSE_MSG(test, src.x1 != 0 || src.x2 != 1 << 16 || in drm_test_rect_clip_scaled_not_clipped()
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/openbmc/u-boot/drivers/serial/
H A Dserial_sh.h2 * Copy and modify from linux/drivers/serial/sh-sci.h
26 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
28 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
38 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
39 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
41 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
49 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
55 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
57 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
65 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
[all …]
/openbmc/u-boot/arch/arm/include/asm/mach-imx/
H A Dregs-gpmi.h1 /* SPDX-License-Identifier: GPL-2.0+ */
9 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
15 #include <asm/mach-imx/regs-common.h>
38 #define GPMI_CTRL0_SFTRST (1 << 31)
39 #define GPMI_CTRL0_CLKGATE (1 << 30)
40 #define GPMI_CTRL0_RUN (1 << 29)
41 #define GPMI_CTRL0_DEV_IRQ_EN (1 << 28)
42 #define GPMI_CTRL0_LOCK_CS (1 << 27)
43 #define GPMI_CTRL0_UDMA (1 << 26)
50 #define GPMI_CTRL0_WORD_LENGTH (1 << 23)
[all …]
/openbmc/qemu/include/hw/arm/
H A Dfsl-imx25.h4 * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
36 #define TYPE_FSL_IMX25 "fsl-imx25"
74 * 0x0000_0000 0x0000_3FFF 16 Kbytes ROM (36 Kbytes)
82 * 0x43F0_0000 0x43F0_3FFF 16 Kbytes AIPS A control registers
83 * 0x43F0_4000 0x43F0_7FFF 16 Kbytes ARM926 platform MAX
84 * 0x43F0_8000 0x43F0_BFFF 16 Kbytes ARM926 platform CLKCTL
85 * 0x43F0_C000 0x43F0_FFFF 16 Kbytes ARM926 platform ETB registers
86 * 0x43F1_0000 0x43F1_3FFF 16 Kbytes ARM926 platform ETB memory
87 * 0x43F1_4000 0x43F1_7FFF 16 Kbytes ARM926 platform AAPE registers
89 * 0x43F8_0000 0x43F8_3FFF 16 Kbytes I2C-1
[all …]
/openbmc/linux/arch/x86/crypto/
H A Daes_ctrby8_avx-x86_64.S1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
19 * https://github.com/intel/intel-ipsec-mb
58 #define XDATA 1
59 #define KEY_128 1
64 .align 16
118 vmovdqa 0*16(p_keys), xkey0
126 vpaddq (ddq_add_1 + 16 * i)(%rip), xtmp, var_xdata
127 .set i, (i +1)
133 .set i, (i +1)
137 .set i, 1
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/openbmc/linux/arch/arm64/lib/
H A Dcopy_template.S1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * http://bazaar.launchpad.net/~linaro-toolchain-dev/cortex-strings/trunk/
18 * x0 - dest
19 * x1 - src
20 * x2 - n
22 * x0 - dest
43 cmp count, #16
44 /*When memory length is less than 16, the accessed are not aligned.*/
55 * dst is less than 16. The memory accesses here are alignment.
57 tbz tmp2, #0, 1f
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/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_ids.c28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
44 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
46 {"TC58NVG2S0F 4G 3.3V 8-bit",
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