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/openbmc/u-boot/arch/x86/cpu/queensbay/
H A DKconfig47 default 0xfffb0000
52 The default base address of 0xfffb0000 indicates that the binary must
53 be located at offset 0xb0000 from the beginning of a 1MB flash device.
/openbmc/u-boot/configs/
H A Dtheadorable-x86-dfi-bt700_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFF00000
7 CONFIG_VGA_BIOS_ADDR=0xfffb0000
H A Dtheadorable-x86-conga-qa3-e3845_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFF00000
8 CONFIG_VGA_BIOS_ADDR=0xfffb0000
H A Dbayleybay_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFF00000
8 CONFIG_VGA_BIOS_ADDR=0xfffb0000
H A Dconga-qeval20-qa3-e3845-internal-uart_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFF00000
3 CONFIG_DEBUG_UART_BASE=0x3f8
11 CONFIG_VGA_BIOS_ADDR=0xfffb0000
H A Dminnowmax_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFF00000
3 CONFIG_DEBUG_UART_BASE=0x3f8
11 CONFIG_VGA_BIOS_ADDR=0xfffb0000
H A Dtheadorable-x86-conga-qa3-e3845-pcie-x4_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFF00000
9 CONFIG_VGA_BIOS_ADDR=0xfffb0000
/openbmc/qemu/hw/hppa/
H A Dhppa_hardware.h7 #define FIRMWARE_START 0xf0000000
8 #define FIRMWARE_END 0xf0800000
10 #define DEVICE_HPA_LEN 0x00100000
12 #define GSC_HPA 0xffc00000
13 #define DINO_HPA 0xfff80000
14 #define DINO_UART_HPA 0xfff83000
15 #define DINO_UART_BASE 0xfff83800
16 #define DINO_SCSI_HPA 0xfff8c000
17 #define LASI_HPA 0xffd00000
18 #define LASI_UART_HPA 0xffd05000
[all …]
/openbmc/linux/drivers/gpu/drm/sti/
H A Dsti_hqvdp_lut.h24 0x0000ffff, 0x00010000, 0x000100ff, 0x00000000,
25 0x00000000, 0x00050000, 0xfffc00ff, 0x00000000,
26 0x00000000, 0x00090000, 0xfff900fe, 0x00000000,
27 0x00000000, 0x0010ffff, 0xfff600fb, 0x00000000,
28 0x00000000, 0x0017fffe, 0xfff400f7, 0x00000000,
29 0x00000000, 0x001ffffd, 0xfff200f2, 0x00000000,
30 0x00000000, 0x0027fffc, 0xfff100ec, 0x00000000,
31 0x00000000, 0x0030fffb, 0xfff000e5, 0x00000000,
32 0x00000000, 0x003afffa, 0xffee00de, 0x00000000,
33 0x00000000, 0x0044fff9, 0xffed00d6, 0x00000000,
[all …]
/openbmc/linux/arch/arm/mach-omap1/
H A Diomap.h31 #define OMAP1_IO_PHYS 0xFFFB0000
32 #define OMAP1_IO_SIZE 0x40000
/openbmc/qemu/tests/functional/
H A Dtest_arm_sx1.py37 CONSOLE_ARGS = 'console=ttyS0,115200 earlycon=uart8250,mmio32,0xfffb0000,115200n8'
43 self.vm.add_args('-append', f'kunit.enable=0 rdinit=/sbin/init {self.CONSOLE_ARGS}')
53 … self.vm.add_args('-append', f'kunit.enable=0 root=/dev/mmcblk0 rootwait {self.CONSOLE_ARGS}')
64 … self.vm.add_args('-append', f'kunit.enable=0 root=/dev/mtdblock3 rootwait {self.CONSOLE_ARGS}')
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Datmel,sama9260-adc.yaml110 reg = <0xfffb0000 0x100>;
111 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
114 atmel,adc-channels-used = <0xff>;
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91sam9rl.h20 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
26 #define ATMEL_ID_USART0 6 /* USART 0 */
31 #define ATMEL_ID_TWI0 11 /* TWI 0 */
34 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
36 #define ATMEL_ID_TC0 16 /* Timer Counter 0 */
50 #define ATMEL_BASE_TCB0 0xfffa0000
51 #define ATMEL_BASE_TC0 0xfffa0000
52 #define ATMEL_BASE_TC1 0xfffa0040
53 #define ATMEL_BASE_TC2 0xfffa0080
54 #define ATMEL_BASE_MCI 0xfffa4000
[all …]
H A Dat91rm9200.h18 #define ATMEL_ID_USART0 6 /* USART 0 */
26 #define ATMEL_ID_SSC0 14 /* Synch. Serial Controller 0 */
29 #define ATMEL_ID_TC0 17 /* Timer Counter 0 */
45 #define ATMEL_USB_HOST_BASE 0x00300000
47 #define ATMEL_BASE_TC 0xFFFA0000
48 #define ATMEL_BASE_UDP 0xFFFB0000
49 #define ATMEL_BASE_MCI 0xFFFB4000
50 #define ATMEL_BASE_TWI 0xFFFB8000
51 #define ATMEL_BASE_EMAC 0xFFFBC000
52 #define ATMEL_BASE_USART 0xFFFC0000 /* 4x 0x4000 Offset */
[all …]
H A Dat91sam9261.h23 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
29 #define ATMEL_ID_USART0 6 /* USART 0 */
34 #define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */
35 #define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */
37 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
40 #define ATMEL_ID_TC0 17 /* Timer Counter 0 */
53 #define ATMEL_BASE_TCB0 0xfffa0000
54 #define ATMEL_BASE_TC0 0xfffa0000
55 #define ATMEL_BASE_TC1 0xfffa0040
56 #define ATMEL_BASE_TC2 0xfffa0080
[all …]
H A Dat91sam9g45.h17 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
24 #define ATMEL_ID_USART0 7 /* USART 0 */
28 #define ATMEL_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
29 #define ATMEL_ID_TWI0 12 /* Two-Wire Interface 0 */
31 #define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */
33 #define ATMEL_ID_SSC0 16 /* Synchronous Serial Controller 0 */
35 #define ATMEL_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
53 #define ATMEL_BASE_UDPHS 0xfff78000
54 #define ATMEL_BASE_TC0 0xfff7c000
55 #define ATMEL_BASE_TC1 0xfff7c040
[all …]
H A Dat91sam9260.h23 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
29 #define ATMEL_ID_USART0 6 /* USART 0 */
34 #define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */
35 #define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */
37 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
40 #define ATMEL_ID_TC0 17 /* Timer Counter 0 */
44 #define ATMEL_ID_EMAC0 21 /* Ethernet 0 */
59 #define ATMEL_BASE_TCB0 0xfffa0000
60 #define ATMEL_BASE_TC0 0xfffa0000
61 #define ATMEL_BASE_TC1 0xfffa0040
[all …]
/openbmc/linux/drivers/net/ethernet/ti/icssg/
H A Dicssg_config.h21 #define PRUETH_PKT_TYPE_CMD 0x10
27 #define PRUETH_RX_FLOW_DATA 0
45 #define ICSSG_FW_MGMT_CMD_HEADER 0x81
46 #define ICSSG_FW_MGMT_FDB_CMD_TYPE 0x03
47 #define ICSSG_FW_MGMT_CMD_TYPE 0x04
48 #define ICSSG_FW_MGMT_PKT 0x80000000
55 ICSSG_EMAC_PORT_DISABLE = 0,
77 #define EMAC_NONE 0xffff0000
78 #define EMAC_PRU0_P_DI 0xffff0004
79 #define EMAC_PRU1_P_DI 0xffff0040
[all …]
/openbmc/qemu/hw/misc/
H A Dlasi.c73 s->ipr = 0; in lasi_chip_read_with_attrs()
87 val = 0; in lasi_chip_read_with_attrs()
95 case LASI_VER: /* only version 0 existed. */ in lasi_chip_read_with_attrs()
97 val = 0; in lasi_chip_read_with_attrs()
131 if (((val & LASI_IRQ_BITS) != val) && (val != 0xffffffff)) { in lasi_chip_write_with_attrs()
139 s->ipr = 0; in lasi_chip_write_with_attrs()
170 if (val == 0x02) { /* immediately power off */ in lasi_chip_write_with_attrs()
236 if ((s->icr & ICR_BUS_ERROR_BIT) == 0) { in lasi_set_irq()
247 s->iar = 0xFFFB0000 + 3; /* CPU_HPA + 3 */ in lasi_reset()
250 s->rtc_ref = 0; in lasi_reset()
[all …]
/openbmc/linux/arch/parisc/kernel/
H A Dsetup.c49 /* boot_args[0] is free-mem start, boot_args[1] is ptr to command line */ in setup_cmdline()
50 if (boot_args[0] < 64) in setup_cmdline()
73 if (boot_args[2] != 0) { in setup_cmdline()
160 * 0, signaling EOF perhaps. This could be used to sequence in c_start()
188 .start = F_EXTEND(0xfff80000),
189 .end = F_EXTEND(0xfffaffff),
195 .start = F_EXTEND(0xfffb0000),
196 .end = F_EXTEND(0xfffdffff),
202 .start = F_EXTEND(0xfffe0000),
203 .end = F_EXTEND(0xffffffff),
[all …]
/openbmc/qemu/hw/pci-host/
H A Ddino.c29 * 0xf0800000 and 0xff000000 to the PCI bus.
37 enabled = (tmp == 0x01); in gsc_to_pci_forwarding()
40 io_addr_en &= ~(BIT(31) | BIT(0)); in gsc_to_pci_forwarding()
47 uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE; in gsc_to_pci_forwarding()
149 s->ipr = 0; in dino_chip_read_with_attrs()
166 val &= ~0x01; /* LSB is hardwired to 0 */ in dino_chip_read_with_attrs()
169 val &= ~0x07; /* 3 LSB are hardwired to 0 */ in dino_chip_read_with_attrs()
172 val &= ~(0x10710E0ul | 8); /* bits 5-7, 24 & 15 reserved */ in dino_chip_read_with_attrs()
220 s->io_fbb_en = val & 0x03; in dino_chip_write_with_attrs()
245 s->ipr = 0; in dino_chip_write_with_attrs()
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dio_mm.h45 #define q40_isa_io_base 0xff400000
46 #define q40_isa_mem_base 0xff800000
53 #define MULTI_ISA 0
63 #define MULTI_ISA 0
72 #define enec_isa_read_base 0xfffa0000
73 #define enec_isa_write_base 0xfffb0000
75 #define ENEC_ISA_IO_B(ioaddr) (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9))
76 #define ENEC_ISA_IO_W(ioaddr) (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9))
77 #define ENEC_ISA_MEM_B(madr) (enec_isa_read_base+((((unsigned long)(madr))&0x7F)<<9))
78 #define ENEC_ISA_MEM_W(madr) (enec_isa_read_base+((((unsigned long)(madr))&0x7F)<<9))
[all …]
/openbmc/linux/include/uapi/linux/
H A Dserial_reg.h19 * DLAB=0
21 #define UART_RX 0 /* In: Receive buffer */
22 #define UART_TX 0 /* Out: Transmit buffer */
25 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
26 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
27 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
28 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
32 #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
35 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
36 #define UART_IIR_ID 0x0e /* Mask for the interrupt ID */
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9261.dtsi38 #size-cells = <0>;
40 cpu@0 {
43 reg = <0>;
49 reg = <0x20000000 0x08000000>;
55 #clock-cells = <0>;
56 clock-frequency = <0>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
68 reg = <0x00300000 0x28000>;
71 ranges = <0 0x00300000 0x28000>;
[all …]
H A Dat91rm9200.dtsi44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x04000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
74 reg = <0x00200000 0x4000>;
77 ranges = <0 0x00200000 0x4000>;
[all …]

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