/openbmc/u-boot/arch/sh/include/asm/ |
H A D | cpu_sh7763.h | 11 #define CCR 0xFF00001C 12 #define CCR_CACHE_INIT 0x0000090b 17 #define SCSMR0 0xFFE00000 21 #define SCSMR1 0xFFE08000 25 #define SCSMR2 0xFFE10000 29 #define WDTST 0xFFCC0000 32 #define TMU_BASE 0xFFD80000
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H A D | cpu_sh7734.h | 11 #define CCR 0xFF00001C 14 #define CCR_CACHE_INIT 0x0000090d 17 #define SCIF0_BASE 0xFFE40000 18 #define SCIF1_BASE 0xFFE41000 19 #define SCIF2_BASE 0xFFE42000 20 #define SCIF3_BASE 0xFFE43000 21 #define SCIF4_BASE 0xFFE44000 22 #define SCIF5_BASE 0xFFE45000 25 #define TMU_BASE 0xFFD80000 28 #define PMMR (0xFFFC0000) [all …]
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H A D | cpu_sh7785.h | 12 #define CCR_CACHE_INIT 0x0000090b 15 #define TRA 0xFF000020 16 #define EXPEVT 0xFF000024 17 #define INTEVT 0xFF000028 20 #define CCR 0xFF00001C 21 #define QACR0 0xFF000038 22 #define QACR1 0xFF00003C 23 #define RAMCR 0xFF000074 27 #define WDTST 0xFFCC0000 28 #define WDTCSR 0xFFCC0004 [all …]
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H A D | cpu_sh7750.h | 14 #define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */ 17 #define CCR_CACHE_INIT 0x0000090B 21 #define PTEH 0xFF000000 22 #define PTEL 0xFF000004 23 #define TTB 0xFF000008 24 #define TEA 0xFF00000C 25 #define MMUCR 0xFF000010 26 #define BASRA 0xFF000014 27 #define BASRB 0xFF000018 28 #define CCR 0xFF00001C [all …]
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H A D | cpu_sh7723.h | 12 #define CCR_CACHE_INIT 0x0000090d 15 #define TRA 0xFF000020 16 #define EXPEVT 0xFF000024 17 #define INTEVT 0xFF000028 20 #define PTEH 0xFF000000 21 #define PTEL 0xFF000004 22 #define TTB 0xFF000008 23 #define TEA 0xFF00000C 24 #define MMUCR 0xFF000010 25 #define PASCR 0xFF000070 [all …]
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H A D | cpu_sh7724.h | 12 #define CCR_CACHE_INIT 0x0000090d 15 #define TRA 0xFF000020 16 #define EXPEVT 0xFF000024 17 #define INTEVT 0xFF000028 20 #define PTEH 0xFF000000 21 #define PTEL 0xFF000004 22 #define TTB 0xFF000008 23 #define TEA 0xFF00000C 24 #define MMUCR 0xFF000010 25 #define PASCR 0xFF000070 [all …]
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H A D | cpu_sh7780.h | 11 #define CCR_CACHE_INIT 0x0000090b 14 #define TRA 0xFF000020 15 #define EXPEVT 0xFF000024 16 #define INTEVT 0xFF000028 19 #define PTEH 0xFF000000 20 #define PTEL 0xFF000004 21 #define TTB 0xFF000008 22 #define TEA 0xFF00000C 23 #define MMUCR 0xFF000010 24 #define PASCR 0xFF000070 [all …]
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/openbmc/linux/Documentation/devicetree/bindings/timer/ |
H A D | renesas,tmu.yaml | 100 reg = <0xffd80000 0x30>;
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/openbmc/u-boot/arch/arm/mach-zynqmp/include/mach/ |
H A D | hardware.h | 10 #define ARASAN_NAND_BASEADDR 0xFF100000 12 #define ZYNQMP_TCM_BASE_ADDR 0xFFE00000 13 #define ZYNQMP_TCM_SIZE 0x40000 15 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 16 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 17 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 20 #define PS_MODE0 BIT(0) 31 #define RESET_REASON_EXTERNAL BIT(0) 35 u32 cpu_r5_ctrl; /* 0x90 */ 37 u32 timestamp_ref_ctrl; /* 0x128 */ [all …]
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/openbmc/linux/arch/sh/kernel/cpu/sh4/ |
H A D | setup-sh4-202.c | 23 DEFINE_RES_MEM(0xffe80000, 0x100), 24 DEFINE_RES_IRQ(evt2irq(0x700)), 25 DEFINE_RES_IRQ(evt2irq(0x720)), 26 DEFINE_RES_IRQ(evt2irq(0x760)), 27 DEFINE_RES_IRQ(evt2irq(0x740)), 32 .id = 0, 45 DEFINE_RES_MEM(0xffd80000, 0x30), 46 DEFINE_RES_IRQ(evt2irq(0x400)), 47 DEFINE_RES_IRQ(evt2irq(0x420)), 48 DEFINE_RES_IRQ(evt2irq(0x440)), [all …]
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H A D | setup-sh7760.c | 17 UNUSED = 0, 44 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 45 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 46 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 47 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0), 48 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0), 49 INTC_VECT(DMAC, 0x6c0), 50 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820), 51 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860), 52 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920), [all …]
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H A D | setup-sh7750.c | 19 [0] = { 20 .start = 0xffc80000, 21 .end = 0xffc80000 + 0x58 - 1, 26 .start = evt2irq(0x480), 43 DEFINE_RES_MEM(0xffe00000, 0x20), 44 DEFINE_RES_IRQ(evt2irq(0x4e0)), 49 .id = 0, 63 DEFINE_RES_MEM(0xffe80000, 0x100), 64 DEFINE_RES_IRQ(evt2irq(0x700)), 82 DEFINE_RES_MEM(0xffd80000, 0x30), [all …]
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/openbmc/linux/arch/sh/kernel/cpu/sh4a/ |
H A D | setup-sh7366.c | 26 DEFINE_RES_MEM(0xffe00000, 0x100), 27 DEFINE_RES_IRQ(evt2irq(0xc00)), 32 .id = 0, 41 [0] = { 43 .start = 0x04470000, 44 .end = 0x04470017, 48 .start = evt2irq(0xe00), 49 .end = evt2irq(0xe60), 56 .id = 0, /* "i2c0" clock */ 66 [0] = { [all …]
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H A D | setup-sh7343.c | 24 DEFINE_RES_MEM(0xffe00000, 0x100), 25 DEFINE_RES_IRQ(evt2irq(0xc00)), 30 .id = 0, 44 DEFINE_RES_MEM(0xffe10000, 0x100), 45 DEFINE_RES_IRQ(evt2irq(0xc20)), 64 DEFINE_RES_MEM(0xffe20000, 0x100), 65 DEFINE_RES_IRQ(evt2irq(0xc40)), 84 DEFINE_RES_MEM(0xffe30000, 0x100), 85 DEFINE_RES_IRQ(evt2irq(0xc60)), 99 [0] = { [all …]
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H A D | setup-sh7763.c | 26 DEFINE_RES_MEM(0xffe00000, 0x100), 27 DEFINE_RES_IRQ(evt2irq(0x700)), 32 .id = 0, 47 DEFINE_RES_MEM(0xffe08000, 0x100), 48 DEFINE_RES_IRQ(evt2irq(0xb80)), 68 DEFINE_RES_MEM(0xffe10000, 0x100), 69 DEFINE_RES_IRQ(evt2irq(0xf00)), 83 [0] = { 84 .start = 0xffe80000, 85 .end = 0xffe80000 + 0x58 - 1, [all …]
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H A D | setup-sh7780.c | 25 DEFINE_RES_MEM(0xffe00000, 0x100), 26 DEFINE_RES_IRQ(evt2irq(0x700)), 31 .id = 0, 46 DEFINE_RES_MEM(0xffe10000, 0x100), 47 DEFINE_RES_IRQ(evt2irq(0xb80)), 65 DEFINE_RES_MEM(0xffd80000, 0x30), 66 DEFINE_RES_IRQ(evt2irq(0x580)), 67 DEFINE_RES_IRQ(evt2irq(0x5a0)), 68 DEFINE_RES_IRQ(evt2irq(0x5c0)), 73 .id = 0, [all …]
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H A D | setup-sh7770.c | 22 DEFINE_RES_MEM(0xff923000, 0x100), 23 DEFINE_RES_IRQ(evt2irq(0x9a0)), 28 .id = 0, 42 DEFINE_RES_MEM(0xff924000, 0x100), 43 DEFINE_RES_IRQ(evt2irq(0x9c0)), 62 DEFINE_RES_MEM(0xff925000, 0x100), 63 DEFINE_RES_IRQ(evt2irq(0x9e0)), 82 DEFINE_RES_MEM(0xff926000, 0x100), 83 DEFINE_RES_IRQ(evt2irq(0xa00)), 102 DEFINE_RES_MEM(0xff927000, 0x100), [all …]
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H A D | setup-sh7734.c | 32 DEFINE_RES_MEM(0xffe40000, 0x100), 33 DEFINE_RES_IRQ(evt2irq(0x8c0)), 38 .id = 0, 53 DEFINE_RES_MEM(0xffe41000, 0x100), 54 DEFINE_RES_IRQ(evt2irq(0x8e0)), 74 DEFINE_RES_MEM(0xffe42000, 0x100), 75 DEFINE_RES_IRQ(evt2irq(0x900)), 95 DEFINE_RES_MEM(0xffe43000, 0x100), 96 DEFINE_RES_IRQ(evt2irq(0x920)), 116 DEFINE_RES_MEM(0xffe44000, 0x100), [all …]
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H A D | setup-sh7723.c | 30 DEFINE_RES_MEM(0xffe00000, 0x100), 31 DEFINE_RES_IRQ(evt2irq(0xc00)), 36 .id = 0, 51 DEFINE_RES_MEM(0xffe10000, 0x100), 52 DEFINE_RES_IRQ(evt2irq(0xc20)), 72 DEFINE_RES_MEM(0xffe20000, 0x100), 73 DEFINE_RES_IRQ(evt2irq(0xc40)), 92 DEFINE_RES_MEM(0xa4e30000, 0x100), 93 DEFINE_RES_IRQ(evt2irq(0x900)), 112 DEFINE_RES_MEM(0xa4e40000, 0x100), [all …]
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H A D | setup-sh7785.c | 27 DEFINE_RES_MEM(0xffea0000, 0x100), 28 DEFINE_RES_IRQ(evt2irq(0x700)), 33 .id = 0, 48 DEFINE_RES_MEM(0xffeb0000, 0x100), 49 DEFINE_RES_IRQ(evt2irq(0x780)), 69 DEFINE_RES_MEM(0xffec0000, 0x100), 70 DEFINE_RES_IRQ(evt2irq(0x980)), 90 DEFINE_RES_MEM(0xffed0000, 0x100), 91 DEFINE_RES_IRQ(evt2irq(0x9a0)), 111 DEFINE_RES_MEM(0xffee0000, 0x100), [all …]
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H A D | setup-sh7722.c | 30 .addr = 0xffe0000c, 32 .mid_rid = 0x21, 35 .addr = 0xffe00014, 37 .mid_rid = 0x22, 40 .addr = 0xffe1000c, 42 .mid_rid = 0x25, 45 .addr = 0xffe10014, 47 .mid_rid = 0x26, 50 .addr = 0xffe2000c, 52 .mid_rid = 0x29, [all …]
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/openbmc/linux/drivers/mtd/maps/ |
H A D | ichxrom.c | 30 #define BIOS_CNTL 0x4e 31 #define FWH_DEC_EN1 0xE3 32 #define FWH_DEC_EN2 0xF0 33 #define FWH_SEL1 0xE8 34 #define FWH_SEL2 0xEE 83 window->phys = 0; in ichxrom_cleanup() 84 window->size = 0; in ichxrom_cleanup() 113 window->phys = 0; in ichxrom_init_one() 115 if (byte == 0xff) { in ichxrom_init_one() 116 window->phys = 0xffc00000; in ichxrom_init_one() [all …]
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H A D | esb2rom.c | 34 #define BIOS_CNTL 0xDC 35 #define BIOS_LOCK_ENABLE 0x02 36 #define BIOS_WRITE_ENABLE 0x01 39 #define FWH_DEC_EN1 0xD8 40 #define FWH_F8_EN 0x8000 41 #define FWH_F0_EN 0x4000 42 #define FWH_E8_EN 0x2000 43 #define FWH_E0_EN 0x1000 44 #define FWH_D8_EN 0x0800 45 #define FWH_D0_EN 0x0400 [all …]
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/openbmc/qemu/contrib/plugins/ |
H A D | howvec.c | 25 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 62 * 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0 66 { " UDEF", "udef", 0xffff0000, 0x00000000, COUNT_NONE}, 67 { " SVE", "sve", 0x1e000000, 0x04000000, COUNT_CLASS}, 68 { "Reserved", "res", 0x1e000000, 0x00000000, COUNT_CLASS}, 70 { " PCrel addr", "pcrel", 0x1f000000, 0x10000000, COUNT_CLASS}, 71 { " Add/Sub (imm,tags)", "asit", 0x1f800000, 0x11800000, COUNT_CLASS}, 72 { " Add/Sub (imm)", "asi", 0x1f000000, 0x11000000, COUNT_CLASS}, 73 { " Logical (imm)", "logi", 0x1f800000, 0x12000000, COUNT_CLASS}, 74 { " Move Wide (imm)", "movwi", 0x1f800000, 0x12800000, COUNT_CLASS}, [all …]
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/openbmc/linux/arch/arm/boot/dts/renesas/ |
H A D | r8a7778.dtsi | 26 #size-cells = <0>; 28 cpu@0 { 31 reg = <0>; 47 ranges = <0 0 0x1c000000>; 53 reg = <0xfde00000 0x400>; 59 #size-cells = <0>; 67 reg = <0xfe438000 0x1000>, 68 <0xfe430000 0x100>; 77 reg = <0xfe78001c 4>, 78 <0xfe780010 4>, [all …]
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