Searched +full:0 +full:xfed80000 (Results 1 – 10 of 10) sorted by relevance
11 #define MCFG_BASE_ADDRESS 0xf000000012 #define MCFG_BASE_SIZE 0x400000014 #define HPET_BASE_ADDRESS 0xfed0000016 #define MCH_BASE_ADDRESS 0xfed1000017 #define MCH_BASE_SIZE 0x800019 #define DMI_BASE_ADDRESS 0xfed1800020 #define DMI_BASE_SIZE 0x100022 #define EP_BASE_ADDRESS 0xfed1900023 #define EP_BASE_SIZE 0x100025 #define EDRAM_BASE_ADDRESS 0xfed80000[all …]
12 #define PMC_BASE_ADDRESS 0xfed0300013 #define PMC_BASE_SIZE 0x40016 #define PUNIT_BASE_ADDRESS 0xfed0500017 #define PUNIT_BASE_SIZE 0x80020 #define ILB_BASE_ADDRESS 0xfed0800021 #define ILB_BASE_SIZE 0x40024 #define SPI_BASE_ADDRESS 0xfed0100025 #define SPI_BASE_SIZE 0x40028 #define RCBA_BASE_ADDRESS 0xfed1c00029 #define RCBA_BASE_SIZE 0x400[all …]
10 (((segbus) & 0xfff) << 20) | \11 (((dev) & 0x1f) << 15) | \12 (((fn) & 0x07) << 12))15 #define LPC_DEV 0x1f16 #define LPC_FUNC 019 #define UART_CONT 0x8032 #define IO_BASE_ADDRESS 0xfed8000036 return IO_BASE_ADDRESS + community * 0x8000 + 0x4400 + in gpio_pconf0()37 family * 0x400 + pad * 8; in gpio_pconf0()44 clrsetbits_le32(pconf0_addr, 0xf << 16, func << 16); in gpio_select_func()[all …]
15 #define SP5100_WDT_MEM_MAP_SIZE 0x0816 #define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */17 #define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */19 #define SP5100_WDT_START_STOP_BIT BIT(0)25 #define SP5100_PM_IOPORTS_SIZE 0x0233 #define SP5100_IO_PM_INDEX_REG 0xCD634 #define SP5100_IO_PM_DATA_REG 0xCD737 #define SP5100_SB_RESOURCE_MMIO_BASE 0x9C39 #define SP5100_PM_WATCHDOG_CONTROL 0x6940 #define SP5100_PM_WATCHDOG_BASE 0x6C[all …]
48 port@0:71 - port@091 reg = <0xfed80000 0x10000>;101 #size-cells = <0>;103 port@0 {104 reg = <0>;
20 #define AMD_FCH_MMIO_BASE 0xFED8000021 #define AMD_FCH_GPIO_BANK0_BASE 0x150022 #define AMD_FCH_GPIO_SIZE 0x030058 return 0; in amd_fch_gpio_direction_input()81 return 0; in amd_fch_gpio_direction_output()136 return 0; in amd_fch_gpio_request()
45 #define APU1_FCH_ACPI_MMIO_BASE 0xFED8000046 #define APU1_FCH_GPIO_BASE (APU1_FCH_ACPI_MMIO_BASE + 0x01BD)47 #define APU1_LEDON 0x0848 #define APU1_LEDOFF 0xC880 { "apu:green:1", LED_ON, APU1_FCH_GPIO_BASE + 0 * APU1_IOSIZE },127 for (i = 0; i < ARRAY_SIZE(apu1_led_profile); i++) { in apu_led_config()151 return 0; in apu_led_config()154 while (i-- > 0) in apu_led_config()190 pdev = platform_device_register_simple(KBUILD_MODNAME, -1, NULL, 0); in apu_led_init()209 for (i = 0; i < ARRAY_SIZE(apu1_led_profile); i++) in apu_led_exit()
29 #define AMDVI_CAPAB_BAR_LOW 0x0430 #define AMDVI_CAPAB_BAR_HIGH 0x0831 #define AMDVI_CAPAB_RANGE 0x0C32 #define AMDVI_CAPAB_MISC 0x1034 #define AMDVI_CAPAB_SIZE 0x1835 #define AMDVI_CAPAB_REG_SIZE 0x0438 #define AMDVI_CAPAB_ID_SEC 0xf51 #define AMDVI_MMIO_DEVICE_TABLE 0x000052 #define AMDVI_MMIO_COMMAND_BASE 0x000853 #define AMDVI_MMIO_EVENT_BASE 0x0010[all …]
20 #clock-cells = <0>;21 clock-frequency = <0>;27 #clock-cells = <0>;28 clock-frequency = <0>;31 cluster0_opp: opp-table-0 {66 #size-cells = <0>;88 a76_0: cpu@0 {90 reg = <0>;102 reg = <0x100>;114 reg = <0x10000>;[all …]
20 #clock-cells = <0>;21 clock-frequency = <0>;26 #size-cells = <0>;28 a76_0: cpu@0 {30 reg = <0>;37 L3_CA76_0: cache-controller-0 {47 #clock-cells = <0>;49 clock-frequency = <0>;54 #clock-cells = <0>;56 clock-frequency = <0>;[all …]