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/openbmc/linux/drivers/gpu/drm/etnaviv/
H A Dcmdstream.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
42 #define FE_OPCODE_LOAD_STATE 0x00000001
43 #define FE_OPCODE_END 0x00000002
44 #define FE_OPCODE_NOP 0x00000003
45 #define FE_OPCODE_DRAW_2D 0x00000004
46 #define FE_OPCODE_DRAW_PRIMITIVES 0x00000005
47 #define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006
48 #define FE_OPCODE_WAIT 0x00000007
49 #define FE_OPCODE_LINK 0x00000008
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8536ds_36b.dts17 #size-cells = <0>;
19 PowerPC,8536@0 {
21 reg = <0>;
28 reg = <0 0 0 0>; // Filled by U-Boot
32 reg = <0xf 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
35 0x2 0x0 0xf 0xffa00000 0x00040000
36 0x3 0x0 0xf 0xffdf0000 0x00008000>;
40 ranges = <0x0 0xf 0xffe00000 0x100000>;
44 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
/openbmc/linux/arch/arm/include/debug/
H A Dsa1100.S10 #define UTCR3 0x0c
11 #define UTDR 0x14
12 #define UTSR1 0x20
13 #define UTCR3_TXE 0x00000002 /* Transmit Enable */
14 #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
15 #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
18 mrc p15, 0, \rp, c1, c0
20 moveq \rp, #0x80000000 @ physical base address
21 movne \rp, #0xf8000000 @ virtual address
28 add \rp, \rp, #0x00050000
[all …]
H A Dvt8500.S10 #define DEBUG_LL_PHYS_BASE 0xD8000000
11 #define DEBUG_LL_VIRT_BASE 0xF8000000
12 #define DEBUG_LL_UART_OFFSET 0x00200000
22 strb \rd, [\rx, #0]
26 1001: ldr \rd, [\rx, #0x1c]
27 ands \rd, \rd, #0x2
H A Dvexpress.S10 #define DEBUG_LL_PHYS_BASE 0x10000000
11 #define DEBUG_LL_UART_OFFSET 0x00009000
13 #define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
14 #define DEBUG_LL_UART_OFFSET_RS1 0x00090000
16 #define DEBUG_LL_UART_PHYS_CRX 0xb0090000
18 #define DEBUG_LL_VIRT_BASE 0xf8000000
27 @ should use UART at 0x10009000
29 @ at 0x1c090000
30 mrc p15, 0, \rp, c0, c0, 0
31 movw \rv, #0xc091
[all …]
/openbmc/u-boot/board/freescale/mpc8544ds/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
15 MAS3_SX|MAS3_SW|MAS3_SR, 0,
16 0, 0, BOOKE_PAGESZ_4K, 0),
17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
18 MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 0, 0, BOOKE_PAGESZ_4K, 0),
20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/openbmc/linux/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/openbmc/linux/Documentation/arch/x86/
H A Dmtrr.rst73 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
74 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
78 # echo "base=0xf8000000 size=0x400000 type=write-combining" >! /proc/mtrr
82 # echo "base=0xf8000000 size=0x400000 type=write-combining" >| /proc/mtrr
87 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
88 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
89 reg02: base=0xf8000000 (3968MB), size= 4MB: write-combining, count=1
91 This is for video RAM at base address 0xf8000000 and size 4 megabytes. To
96 (--) S3: PCI: 968 rev 0, Linear FB @ 0xf8000000
107 That's 4 megabytes, which is 0x400000 bytes (in hexadecimal).
[all …]
/openbmc/u-boot/include/configs/
H A DMPC8568MDS.h40 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
41 #define CONFIG_SYS_MEMTEST_END 0x00400000
43 #define CONFIG_SYS_CCSRBAR 0xe0000000
51 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
60 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
76 * Boot from BR0/OR0 bank at 0xff00_0000
77 * Alternate BR1/OR1 bank at 0xff80_0000
80 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
81 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
[all …]
H A DMPC8541CDS.h35 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
36 #define CONFIG_SYS_MEMTEST_END 0x00400000
38 #define CONFIG_SYS_CCSRBAR 0xe0000000
45 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
47 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
54 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
72 * Boot from BR0/OR0 bank at 0xff00_0000
73 * Alternate BR1/OR1 bank at 0xff80_0000
76 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
77 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
[all …]
H A DMPC8555CDS.h35 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
36 #define CONFIG_SYS_MEMTEST_END 0x00400000
38 #define CONFIG_SYS_CCSRBAR 0xe0000000
45 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
47 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
54 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
70 * Boot from BR0/OR0 bank at 0xff00_0000
71 * Alternate BR1/OR1 bank at 0xff80_0000
74 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
75 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
[all …]
H A Drk3399_common.h19 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000
20 #define CONFIG_SYS_LOAD_ADDR 0x00800800
21 #define CONFIG_SPL_STACK 0xff8effff
22 #define CONFIG_SPL_TEXT_BASE 0xff8c2000
23 #define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000
25 #define CONFIG_SPL_BSS_START_ADDR 0xff8e0000
26 #define CONFIG_SPL_BSS_MAX_SIZE 0x10000
38 #define CONFIG_SYS_SDRAM_BASE 0
39 #define SDRAM_MAX_SIZE 0xf8000000
44 "scriptaddr=0x00500000\0" \
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dbrcm,stb-pcie.yaml144 reg = <0x0 0x7d500000 0x9310>;
152 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
153 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
154 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
155 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
156 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
160 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
161 dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
162 <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
164 brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
[all …]
/openbmc/u-boot/board/sbc8641d/
H A Dlaw.c16 * 0x0000_0000 DDR 256M
17 * 0x1000_0000 DDR2 256M
18 * 0x8000_0000 PCIE1 MEM 512M
19 * 0xa000_0000 PCIE2 MEM 512M
20 * 0xc000_0000 RapidIO 512M
21 * 0xe200_0000 PCIE1 IO 16M
22 * 0xe300_0000 PCIE2 IO 16M
23 * 0xf800_0000 CCSRBAR 2M
24 * 0xfe00_0000 FLASH (boot bank) 32M
32 SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dsama5d3.h18 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
30 #define ATMEL_ID_USART0 12 /* USART 0 */
36 #define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */
39 #define ATMEL_ID_MCI0 21 /* High Speed Multimedia Card Interface 0 */
42 #define ATMEL_ID_SPI0 24 /* Serial Peripheral Interface 0 */
56 #define ATMEL_ID_SSC0 38 /* Synchronous Serial Controller 0 */
70 #define ARCH_ID_SAMA5D3 0x8a5c07c0
71 #define ARCH_EXID_SAMA5D31 0x00444300
72 #define ARCH_EXID_SAMA5D33 0x00414300
73 #define ARCH_EXID_SAMA5D34 0x00414301
[all …]
/openbmc/linux/sound/isa/gus/
H A Dgus_volume.c24 while (e > 0 && tmp < (1 << e)) in snd_gf1_lvol_to_gvol_raw()
33 if (m > 0) { in snd_gf1_lvol_to_gvol_raw()
43 #if 0
51 return 0;
81 vol_rates[0] :
83 for (i = 0; i < 3; i++) {
95 return (range << 6) | (increment & 0x3f);
98 #endif /* 0 */
105 if (freq16 & 0xf8000000) { in snd_gf1_translate_freq()
106 freq16 = ~0xf8000000; in snd_gf1_translate_freq()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Daxis.txt23 reg = <0xf8000000 0x48>;
/openbmc/qemu/tests/qtest/
H A Dxlnx-canfd-test.c33 #define CANFD0_BASE_ADDR 0xff060000
34 #define CANFD1_BASE_ADDR 0xff070000
37 #define R_SRR_OFFSET 0x00
38 #define R_MSR_OFFSET 0x04
39 #define R_FILTER_CONTROL_REGISTER 0xe0
40 #define R_SR_OFFSET 0x18
41 #define R_ISR_OFFSET 0x1c
42 #define R_IER_OFFSET 0x20
43 #define R_ICR_OFFSET 0x24
44 #define R_TX_READY_REQ_REGISTER 0x90
[all …]
/openbmc/qemu/hw/hppa/
H A Dhppa_hardware.h7 #define FIRMWARE_START 0xf0000000
8 #define FIRMWARE_END 0xf0800000
10 #define DEVICE_HPA_LEN 0x00100000
12 #define GSC_HPA 0xffc00000
13 #define DINO_HPA 0xfff80000
14 #define DINO_UART_HPA 0xfff83000
15 #define DINO_UART_BASE 0xfff83800
16 #define DINO_SCSI_HPA 0xfff8c000
17 #define LASI_HPA 0xffd00000
18 #define LASI_UART_HPA 0xffd05000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dhisilicon,hi655x.txt19 - #clock-cells: From common clock binding; shall be set to 0
28 reg = <0x0 0xf8000000 0x0 0x1000>;
32 #clock-cells = <0>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dartpec6.txt30 #clock-cells = <0>;
38 reg = <0xf8000000 0x48>;
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9x5_can.dtsi17 reg = <0xf8000000 0x300>;
20 pinctrl-0 = <&pinctrl_can0_rx_tx>;
28 reg = <0xf8004000 0x300>;
31 pinctrl-0 = <&pinctrl_can1_rx_tx>;
/openbmc/u-boot/board/sbc8548/
H A Dlaw.c16 * 0x0000_0000 0x0fff_ffff DDR 256M
17 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
18 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
19 * 0xe000_0000 0xe000_ffff CCSR 1M
20 * 0xe200_0000 0xe27f_ffff PCI1 IO 8M
21 * 0xe280_0000 0xe2ff_ffff PCIe IO 8M
22 * 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M
23 * 0xf000_0000 0xf7ff_ffff SDRAM 128M
24 * 0xf8b0_0000 0xf80f_ffff EEPROM 1M
25 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dat91sam9x5_can.dtsi19 #clock-cells = <0>;
24 #clock-cells = <0>;
32 reg = <0xf8000000 0x300>;
35 pinctrl-0 = <&pinctrl_can0_rx_tx>;
43 reg = <0xf8004000 0x300>;
46 pinctrl-0 = <&pinctrl_can1_rx_tx>;

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