Searched +full:0 +full:xe6150138 (Results 1 – 6 of 6) sorted by relevance
14 #define RWDT_BASE 0xE602000015 #define SWDT_BASE 0xE603000016 #define LBSC_BASE 0xEE22020017 #define TMU_BASE 0xE61E000018 #define GPIO5_BASE 0xE605500021 #define SCIF0_BASE 0xE6E6000022 #define SCIF1_BASE 0xE6E6800023 #define SCIF2_BASE 0xE6E8800024 #define SCIF3_BASE 0xE6C5000025 #define SCIF4_BASE 0xE6C40000[all …]
14 #define RWDT_BASE 0xE602000015 #define SWDT_BASE 0xE603000016 #define LBSC_BASE 0xFEC0020017 #define DBSC3_0_BASE 0xE679000018 #define DBSC3_1_BASE 0xE67A000019 #define TMU_BASE 0xE61E000020 #define GPIO5_BASE 0xE605500021 #define SH_QSPI_BASE 0xE6B1000024 #define SCIF0_BASE 0xE6E6000025 #define SCIF1_BASE 0xE6E68000[all …]
18 and the clock index in the group, from 0 to 31.69 reg = <0xe6150138 4>, <0xe6150040 4>;
20 #size-cells = <0>;21 cpu@0 {24 reg = <0x0>;35 reg = <0xc2800000 0x1000>,36 <0xc2000000 0x1000>;41 reg = <0xf0100000 0x1000>;53 reg = <0xfe400000 0x400>;68 reg = <0xfe910000 0x3000>;77 reg = <0xfe914000 0x3000>;87 reg = <0xe6138000 0x170>;[all …]
21 #size-cells = <0>;23 cpu0: cpu@0 {26 reg = <0>;33 L2_CA15: cache-controller-0 {65 reg = <0 0xe6790000 0 0x10000>;71 reg = <0 0xe67a0000 0 0x10000>;77 #size-cells = <0>;79 reg = <0 0xe60b0000 0 0x428>;89 reg = <0 0xe6130000 0 0x1004>;108 reg = <0 0xe61c0000 0 0x200>;[all …]
20 #size-cells = <0>;22 cpu0: cpu@0 {25 reg = <0>;44 reg = <0xf0000200 0x100>;51 reg = <0xf0000600 0x20>;60 reg = <0xf0001000 0x1000>,61 <0xf0000100 0x100>;66 reg = <0xf0100000 0x1000>;78 reg = <0xfb400000 0x400>;87 reg = <0xfe400000 0x400>;[all …]