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/openbmc/linux/arch/mips/jazz/
H A Dirq.c62 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); in init_r4030_ints()
69 * driver compatibility reasons interrupts 0 - 15 to be the i8259
79 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ in arch_init_irq()
80 add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K); in arch_init_irq()
81 /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */ in arch_init_irq()
82 add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M); in arch_init_irq()
83 /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */ in arch_init_irq()
84 add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M); in arch_init_irq()
106 if (likely(irq > 0)) in plat_irq_dispatch()
H A Dsetup.c33 .start = 0x00,
34 .end = 0x1f,
38 .start = 0x40,
39 .end = 0x5f,
43 .start = 0x80,
44 .end = 0x8f,
48 .start = 0xc0,
49 .end = 0xdf,
59 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ in plat_mem_setup()
60 add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K); in plat_mem_setup()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-spear/
H A Dhardware.h10 #define CONFIG_SYS_USBD_BASE 0xE1100000
11 #define CONFIG_SYS_PLUG_BASE 0xE1200000
12 #define CONFIG_SYS_FIFO_BASE 0xE1000800
13 #define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000
14 #define CONFIG_SYS_UHC1_EHCI_BASE 0xE2000000
15 #define CONFIG_SYS_SMI_BASE 0xFC000000
16 #define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
17 #define CONFIG_SPEAR_TIMERBASE 0xFC800000
18 #define CONFIG_SPEAR_MISCBASE 0xFCA80000
19 #define CONFIG_SPEAR_ETHBASE 0xE0800000
[all …]
/openbmc/linux/arch/arm/mach-bcm/
H A Dboard_bcm281xx.c11 #define SECWDOG_OFFSET 0x00000000
12 #define SECWDOG_RESERVED_MASK 0xe2000000
13 #define SECWDOG_WD_LOAD_FLAG_MASK 0x10000000
14 #define SECWDOG_EN_MASK 0x08000000
15 #define SECWDOG_SRSTEN_MASK 0x04000000
17 #define SECWDOG_COUNT_SHIFT 0
30 base = of_iomap(np_wdog, 0); in bcm281xx_restart()
41 (0x15 << SECWDOG_CLKS_SHIFT) | in bcm281xx_restart()
42 (0x8 << SECWDOG_COUNT_SHIFT); in bcm281xx_restart()
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A D83xx-512x-pci.txt12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Darm,pl353-nand-r2p1.yaml37 reg = <0xe000e000 0x0001000>;
40 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
41 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
42 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
46 nfc0: nand-controller@0,0 {
48 reg = <0 0 0x1000000>;
50 #size-cells = <0>;
/openbmc/qemu/docs/system/arm/
H A Dxlnx-zynq.rst17 - SMC SRAM@0xe2000000 64MB
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dcpu.h12 #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
13 #define SSP0_BASE 0x20084000 /* SSP0 registers base */
14 #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
15 #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
16 #define DMA_BASE 0x31000000 /* DMA controller registers base */
17 #define USB_BASE 0x31020000 /* USB registers base */
18 #define LCD_BASE 0x31040000 /* LCD registers base */
19 #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
20 #define EMC_BASE 0x31080000 /* EMC configuration registers base */
23 #define CLK_PM_BASE 0x40004000 /* System control registers base */
[all …]
/openbmc/u-boot/include/configs/
H A Dve8313.h33 #define CONFIG_SYS_IMMR 0xE0000000
35 #define CONFIG_SYS_MEMTEST_START 0x00001000
36 #define CONFIG_SYS_MEMTEST_END 0x07000000
48 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
63 /* 0x80840102 */
65 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
66 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
67 | (0 << TIMING_CFG0_WRT_SHIFT) \
74 /* 0x0e720802 */
83 /* 0x26256222 */
[all …]
H A Dids8313.h29 #define CONFIG_SYS_IMMR 0xF0000000
31 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
32 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
39 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
55 #define CONFIG_SYS_SICRH 0x00000000
60 #define CONFIG_SYS_HID0_INIT 0x000000000
65 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
71 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
72 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
73 #define CONFIG_SYS_GBL_DATA_SIZE 0x100
[all …]
H A DMPC8541CDS.h35 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
36 #define CONFIG_SYS_MEMTEST_END 0x00400000
38 #define CONFIG_SYS_CCSRBAR 0xe0000000
45 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
47 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
54 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
72 * Boot from BR0/OR0 bank at 0xff00_0000
73 * Alternate BR1/OR1 bank at 0xff80_0000
76 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
77 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
[all …]
H A DMPC8555CDS.h35 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
36 #define CONFIG_SYS_MEMTEST_END 0x00400000
38 #define CONFIG_SYS_CCSRBAR 0xe0000000
45 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
47 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
54 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
70 * Boot from BR0/OR0 bank at 0xff00_0000
71 * Alternate BR1/OR1 bank at 0xff80_0000
74 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
75 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
[all …]
H A DMPC8540ADS.h21 * default CCARBAR is at 0xff700000
61 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
62 #define CONFIG_SYS_MEMTEST_END 0x00400000
64 #define CONFIG_SYS_CCSRBAR 0xe0000000
71 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
73 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
80 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
84 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
85 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
86 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
[all …]
H A DMPC8568MDS.h40 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
41 #define CONFIG_SYS_MEMTEST_END 0x00400000
43 #define CONFIG_SYS_CCSRBAR 0xe0000000
51 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
60 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
76 * Boot from BR0/OR0 bank at 0xff00_0000
77 * Alternate BR1/OR1 bank at 0xff80_0000
80 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
81 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
[all …]
H A DMPC8560ADS.h24 * default CCARBAR is at 0xff700000
60 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
61 #define CONFIG_SYS_MEMTEST_END 0x00400000
63 #define CONFIG_SYS_CCSRBAR 0xe0000000
70 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
72 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
79 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
83 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
84 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
85 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
[all …]
H A Dvme8349.h55 #define CONFIG_SYS_IMMR 0xE0000000
58 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
59 #define CONFIG_SYS_MEMTEST_END 0x00100000
67 #define SPD_EEPROM_ADDRESS 0x54
83 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
92 /* 0x80080001 */
98 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
114 /* 0xffc06ff7 */
118 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
134 /* 0xf8006ff7 */
[all …]
H A DMPC8548CDS.h52 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
53 #define CONFIG_SYS_MEMTEST_END 0x00400000
55 #define CONFIG_SYS_CCSRBAR 0xe0000000
64 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
66 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
73 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
85 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
86 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
87 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
88 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
[all …]
H A DMPC8313ERDB.h30 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
32 #define CONFIG_SPL_PAD_TO 0x4000
35 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
36 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
38 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
39 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
73 #define CONFIG_SYS_IMMR 0xE0000000
79 #define CONFIG_SYS_MEMTEST_START 0x00001000
80 #define CONFIG_SYS_MEMTEST_END 0x07f00000
88 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
[all …]
H A DMPC8349ITX.h11 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
12 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
13 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
14 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
15 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
16 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
17 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
18 0xF001_0000-0xF001_FFFF Local bus expansion slot
19 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
20 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
[all …]
H A Dsbc8349.h49 #define CONFIG_SYS_IMMR 0xE0000000
52 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
53 #define CONFIG_SYS_MEMTEST_END 0x00100000
75 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
86 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
97 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
98 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
99 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
100 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
105 #define CONFIG_SYS_DDR_MODE 0x00000023
[all …]
/openbmc/u-boot/board/sbc8548/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
15 MAS3_SX|MAS3_SW|MAS3_SR, 0,
16 0, 0, BOOKE_PAGESZ_4K, 0),
17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 MAS3_SX|MAS3_SW|MAS3_SR, 0,
20 0, 0, BOOKE_PAGESZ_4K, 0),
21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
23 MAS3_SX|MAS3_SW|MAS3_SR, 0,
24 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl35x-smc.yaml33 pattern: "^memory-controller@[0-9a-f]+$"
69 - description: Combined or Memory interface 0 IRQ
73 "@[0-7],[a-f0-9]+$":
91 minimum: 0
141 reg = <0xe000e000 0x0001000>;
144 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
145 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
146 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
150 nfc0: nand-controller@0,0 {
152 reg = <0 0 0x1000000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,lan966x-switch.yaml20 pattern: "^switch@[0-9a-f]+$"
68 const: 0
73 "^port@[0-9a-f]+$":
83 const: 0
143 reg = <0xe0000000 0x0100000>,
144 <0xe2000000 0x0800000>;
148 resets = <&switch_reset 0>;
152 #size-cells = <0>;
154 port0: port@0 {
155 reg = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Dcn9131-db.dtsi21 cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
24 pinctrl-0 = <&cp1_xhci0_vbus_pins>;
45 pinctrl-0 = <&cp1_sfp_pins>;
61 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
62 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
90 phys = <&cp1_comphy4 0>;
106 pinctrl-0 = <&cp1_i2c0_pins>;
113 pinctrl-0 = <&cp1_pcie_reset_pins>;
116 marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
119 phys = <&cp1_comphy0 0
[all …]
/openbmc/u-boot/board/maxbcm/
H A Dmaxbcm.c19 #define DEV_CS0_BASE 0xe0000000
20 #define DEV_CS1_BASE 0xe1000000
21 #define DEV_CS2_BASE 0xe2000000
22 #define DEV_CS3_BASE 0xe3000000
26 {0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */
27 {0x00001404, 0x30000820}, /* Dunit Control Low Register */
28 {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */
29 {0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */
30 {0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */
31 {0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */
[all …]

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