/openbmc/linux/drivers/thunderbolt/ |
H A D | xdomain.c | 81 UUID_INIT(0xb638d70e, 0x42ff, 0x40bb, 82 0x97, 0xc2, 0x90, 0xe2, 0xc0, 0xb2, 0xff, 0x07); 126 req->result.err = 0; in tb_xdomain_copy() 155 * @xd: XDomain to send the message 163 * Return: %0 in case of success and negative errno in case of failure 165 int tb_xdomain_response(struct tb_xdomain *xd, const void *response, in tb_xdomain_response() argument 168 return __tb_xdomain_response(xd->tb->ctl, response, size, type); in tb_xdomain_response() 202 * @xd: XDomain to send the request 215 * Return: %0 in case of success and negative errno in case of failure 217 int tb_xdomain_request(struct tb_xdomain *xd, const void *request, in tb_xdomain_request() argument [all …]
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H A D | icm.c | 26 #define PCIE2CIO_CMD 0x30 35 #define PCIE2CIO_WRDATA 0x34 36 #define PCIE2CIO_RDDATA 0x38 38 #define PHY_PORT_CS1 0x37 74 * @max_boot_acl: Maximum number of preboot ACL entries (%0 if not supported) 137 #define EP_NAME_INTEL_VSS 0x10 149 #define INTEL_VSS_FLAGS_RTD3 BIT(0) 198 return link ? ((link - 1) ^ 0x01) + 1 : 0; in dual_link_from_link() 209 return depth ? route & ~(0xffULL << (depth - 1) * TB_ROUTE_SHIFT) : 0; in get_parent_route() 223 return 0; in pci2cio_wait_completion() [all …]
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H A D | dma_test.c | 19 #define DMA_TEST_DATA_PATTERN 0x0123456789abcdefLL 72 * @xd: XDomain the service belongs to 81 * @link_speed: Expected link speed (Gb/s), %0 to use whatever is negotiated 82 * @link_width: Expected link width (Gb/s), %0 to use whatever is negotiated 94 struct tb_xdomain *xd; member 116 UUID_INIT(0x3188cd10, 0x6523, 0x4a5a, 117 0xa6, 0x82, 0xfd, 0xca, 0x07, 0xa2, 0x48, 0xd8); 125 tb_xdomain_release_in_hopid(dt->xd, dt->rx_hopid); in dma_test_free_rings() 130 tb_xdomain_release_out_hopid(dt->xd, dt->tx_hopid); in dma_test_free_rings() 139 struct tb_xdomain *xd = dt->xd; in dma_test_start_rings() local [all …]
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/openbmc/linux/fs/jffs2/ |
H A D | xattr.c | 32 * is_xattr_datum_unchecked(c, xd) 34 * unchecked, it returns 0. 35 * unload_xattr_datum(c, xd) 41 * do_verify_xattr_datum(c, xd) 45 * 0 will be returned, if success. An negative return value means recoverable error, and 48 * do_load_xattr_datum(c, xd) 51 * load_xattr_datum(c, xd) 53 * If xd need to call do_verify_xattr_datum() at first, it's called before calling 55 * save_xattr_datum(c, xd) 56 * is used to write xdatum to medium. xd->version will be incremented. [all …]
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H A D | malloc.c | 38 0, 0, NULL); in jffs2_create_slab_caches() 44 0, SLAB_HWCACHE_ALIGN, NULL); in jffs2_create_slab_caches() 50 0, SLAB_HWCACHE_ALIGN, NULL); in jffs2_create_slab_caches() 56 0, 0, NULL); in jffs2_create_slab_caches() 62 0, 0, NULL); in jffs2_create_slab_caches() 68 0, 0, NULL); in jffs2_create_slab_caches() 74 0, 0, NULL); in jffs2_create_slab_caches() 81 0, 0, NULL); in jffs2_create_slab_caches() 87 0, 0, NULL); in jffs2_create_slab_caches() 92 return 0; in jffs2_create_slab_caches() [all …]
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/openbmc/qemu/tcg/loongarch64/ |
H A D | tcg-insn-defs.c.inc | 12 OPC_MOVGR2SCR = 0x00000800, 13 OPC_MOVSCR2GR = 0x00000c00, 14 OPC_CLZ_W = 0x00001400, 15 OPC_CTZ_W = 0x00001c00, 16 OPC_CLZ_D = 0x00002400, 17 OPC_CTZ_D = 0x00002c00, 18 OPC_REVB_2H = 0x00003000, 19 OPC_REVB_2W = 0x00003800, 20 OPC_REVB_D = 0x00003c00, 21 OPC_SEXT_H = 0x00005800, [all …]
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/openbmc/linux/drivers/dma/ |
H A D | uniphier-xdmac.c | 20 #define XDMAC_CH_WIDTH 0x100 22 #define XDMAC_TFA 0x08 24 #define XDMAC_TFA_MASK GENMASK(5, 0) 25 #define XDMAC_SADM 0x10 29 #define XDMAC_SADM_SAM_INC 0 30 #define XDMAC_DADM 0x14 35 #define XDMAC_EXSAD 0x18 36 #define XDMAC_EXDAD 0x1c 37 #define XDMAC_SAD 0x20 38 #define XDMAC_DAD 0x24 [all …]
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/openbmc/linux/arch/powerpc/sysdev/xive/ |
H A D | common.c | 43 #define DBG_VERBOSE(fmt...) do { } while(0) 92 static bool xive_is_store_eoi(struct xive_irq_data *xd) in xive_is_store_eoi() argument 94 return xd->flags & XIVE_IRQ_FLAG_STORE_EOI && xive_store_eoi; in xive_is_store_eoi() 99 * or 0 if there is no new entry. 108 return 0; in xive_read_eq() 113 return 0; in xive_read_eq() 121 if (q->idx == 0) in xive_read_eq() 125 return cur & 0x7fffffff; in xive_read_eq() 135 * (0xff if none) and return what was found (0 if none). 153 u32 irq = 0; in xive_scan_interrupts() [all …]
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/openbmc/qemu/tests/tcg/i386/ |
H A D | test-i386-f2xm1.c | 14 { 0x4.1481697ac693aa6p-4L, 0x3.17ec9f8454896518p-4L, 0x3.17ec9f845489651cp-4L }, 15 { -0xd.84a873b14b9c0e2p-4L, -0x7.1788c46ac260d948p-4L, -0x7.1788c46ac260d94p-4L }, 16 { 0xa.a3dc18b1eff7e8ap-188L, 0x7.6009241b9e21523p-188L, 0x7.6009241b9e215238p-188L }, 17 { -0xe.846aeb6f58174d5p-92L, -0xa.1006405817acc33p-92L, -0xa.1006405817acc32p-92L }, 18 { 0x5.4459f2ac77bb0978p-4L, 0x4.19d3ce7fd5b90ac8p-4L, 0x4.19d3ce7fd5b90adp-4L }, 19 { -0xb.79bece734a62216p-4L, -0x6.4489a7fc150c0fp-4L, -0x6.4489a7fc150c0ef8p-4L }, 20 { 0xa.ab48f9ef732f5c4p-4L, 0x9.66acd7d4b7cf015p-4L, 0x9.66acd7d4b7cf016p-4L }, 21 { -0xb.8204e63359a46e6p-4L, -0x6.48060f0a504e3488p-4L, -0x6.48060f0a504e348p-4L }, 22 { 0xd.c732865701ae935p-4L, 0xd.103bc1a15cd9f71p-4L, 0xd.103bc1a15cd9f72p-4L }, 23 { -0x1.6296e8ff499827a2p-4L, -0xe.e8dc973f0bce9d1p-8L, -0xe.e8dc973f0bce9dp-8L }, [all …]
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H A D | test-i386-fpatan.c | 10 { -__builtin_infl(), -__builtin_infl(), -0x2.5b2f8fe6643a46ap+0L, -0x2.5b2f8fe6643a469cp+0L }, 11 { -__builtin_infl(), -1.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L }, 12 { -__builtin_infl(), -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L }, 13 { -__builtin_infl(), 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L }, 14 { -__builtin_infl(), 1.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L }, 15 { -__builtin_infl(), __builtin_infl(), 0x2.5b2f8fe6643a469cp+0L, 0x2.5b2f8fe6643a46ap+0L }, 16 { -1.0L, -__builtin_infl(), -0x1.921fb54442d1846ap+0L, -0x1.921fb54442d18468p+0L }, 17 { -1.0L, -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L }, 18 { -1.0L, 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L }, 19 { -1.0L, __builtin_infl(), 0x1.921fb54442d18468p+0L, 0x1.921fb54442d1846ap+0L }, [all …]
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/openbmc/linux/drivers/net/thunderbolt/ |
H A D | main.c | 36 #define TBNET_E2E BIT(0) 49 #define TBNET_L0_PORT_NUM(route) ((route) & GENMASK(5, 0)) 60 * supported then @frame_id is filled, otherwise it stays %0. 92 #define TBIP_HDR_LENGTH_MASK GENMASK(5, 0) 151 * @xd: XDomain the service belongs to 182 struct tb_xdomain *xd; member 206 UUID_INIT(0xc66189ca, 0x1cce, 0x4195, 207 0xbd, 0xb8, 0x49, 0x59, 0x2e, 0x5f, 0x5a, 0x4f); 211 UUID_INIT(0x798f589e, 0x3616, 0x8a47, 212 0x97, 0xc6, 0x56, 0x64, 0xa9, 0x20, 0xc8, 0xdd); [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/ |
H A D | mmhub_3_0_1_sh_mask.h | 29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_3_0_0_sh_mask.h | 29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_3_0_2_sh_mask.h | 29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_2_3_0_sh_mask.h | 27 …RDCLI0__VIRT_CHAN__SHIFT 0x0 28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 29 …RDCLI0__URG_HIGH__SHIFT 0x4 30 …RDCLI0__URG_LOW__SHIFT 0x8 31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 32 …RDCLI0__MAX_BW__SHIFT 0xd 33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 34 …DCLI0__MIN_BW__SHIFT 0x16 35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 36 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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/openbmc/linux/include/linux/ |
H A D | thunderbolt.h | 113 TB_PROPERTY_TYPE_UNKNOWN = 0x00, 114 TB_PROPERTY_TYPE_DIRECTORY = 0x44, 115 TB_PROPERTY_TYPE_DATA = 0x64, 116 TB_PROPERTY_TYPE_TEXT = 0x74, 117 TB_PROPERTY_TYPE_VALUE = 0x76, 182 TB_LINK_WIDTH_SINGLE = BIT(0), 274 int tb_xdomain_lane_bonding_enable(struct tb_xdomain *xd); 275 void tb_xdomain_lane_bonding_disable(struct tb_xdomain *xd); 276 int tb_xdomain_alloc_in_hopid(struct tb_xdomain *xd, int hopid); 277 void tb_xdomain_release_in_hopid(struct tb_xdomain *xd, int hopid); [all …]
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/openbmc/linux/drivers/mtd/nand/raw/ |
H A D | sm_common.c | 4 * Common routines & support for xD format 21 return 0; in oob_sm_ooblayout_ecc() 28 case 0: in oob_sm_ooblayout_free() 30 oobregion->offset = 0; in oob_sm_ooblayout_free() 47 return 0; in oob_sm_ooblayout_free() 68 oobregion->offset = 0; in oob_sm_small_ooblayout_ecc() 70 return 0; in oob_sm_small_ooblayout_ecc() 77 case 0: in oob_sm_small_ooblayout_free() 91 return 0; in oob_sm_small_ooblayout_free() 107 oob.block_status = 0x0F; in sm_block_markbad() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/ |
H A D | dpcs_4_2_3_sh_mask.h | 31 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 32 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL 34 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 35 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL 40 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 41 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL 43 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 44 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL 49 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 50 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL [all …]
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H A D | dpcs_3_1_4_sh_mask.h | 33 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0 34 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1 35 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2 36 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3 37 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4 38 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x7 39 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8 40 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0x9 41 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xa 42 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xb [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8ulp-pinfunc.h | 13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0 14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1 15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0 16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1 17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0 18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0 19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0 20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0 21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0 22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0 [all …]
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/openbmc/qemu/scripts/ |
H A D | xen-detect.c | 10 xendevicemodel_handle *xd; in main() local 13 xd = xendevicemodel_open(0, 0); in main() 14 xendevicemodel_pin_memory_cacheattr(xd, 0, 0, 0, 0); in main() 16 xfmem = xenforeignmemory_open(0, 0); in main() 17 xenforeignmemory_map_resource(xfmem, 0, 0, 0, 0, 0, NULL, 0, 0); in main() 19 return 0; in main() 29 xfmem = xenforeignmemory_open(0, 0); in main() 30 xenforeignmemory_map2(xfmem, 0, 0, 0, 0, 0, 0, 0); in main() 31 xentoolcore_restrict_all(0); in main() 33 return 0; in main() [all …]
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/openbmc/linux/sound/pci/au88x0/ |
H A D | au88x0_wt.h | 12 /* WT channels are grouped in banks. Each bank has 0x20 channels. */ 13 /* Bank register address boundary is 0x8000 */ 15 #define NR_WT_PB 0x20 18 #define WT_BAR(x) (((x)&0xffe0)<<0x8) 21 #define WT_CTRL(bank) (((((bank)&1)<<0xd) + 0x00)<<2) /* 0x0000 */ 22 #define WT_SRAMP(bank) (((((bank)&1)<<0xd) + 0x01)<<2) /* 0x0004 */ 23 #define WT_DSREG(bank) (((((bank)&1)<<0xd) + 0x02)<<2) /* 0x0008 */ 24 #define WT_MRAMP(bank) (((((bank)&1)<<0xd) + 0x03)<<2) /* 0x000c */ 25 #define WT_GMODE(bank) (((((bank)&1)<<0xd) + 0x04)<<2) /* 0x0010 */ 26 #define WT_ARAMP(bank) (((((bank)&1)<<0xd) + 0x05)<<2) /* 0x0014 */ [all …]
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/openbmc/linux/drivers/gpio/ |
H A D | gpio-104-dio-48e.c | 32 module_param_hw_array(base, uint, ioport, &num_dio48e, 0); 37 module_param_hw_array(irq, uint, irq, &num_irq, 0); 40 #define DIO48E_ENABLE_INTERRUPT 0xB 42 #define DIO48E_ENABLE_COUNTER_TIMER_ADDRESSING 0xD 44 #define DIO48E_CLEAR_INTERRUPT 0xF 49 regmap_reg_range(0x0, 0x9), regmap_reg_range(0xB, 0xB), 50 regmap_reg_range(0xD, 0xD), regmap_reg_range(0xF, 0xF), 53 regmap_reg_range(0x0, 0x2), regmap_reg_range(0x4, 0x6), 54 regmap_reg_range(0xB, 0xB), regmap_reg_range(0xD, 0xD), 55 regmap_reg_range(0xF, 0xF), [all …]
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/openbmc/linux/tools/arch/x86/kcpuid/ |
H A D | cpuid.csv | 5 0, 0, EAX, 31:0, max_basic_leafs, Max input value for supported subleafs 8 1, 0, EAX, 3:0, stepping, Stepping ID 9 1, 0, EAX, 7:4, model, Model 10 1, 0, EAX, 11:8, family, Family ID 11 1, 0, EAX, 13:12, processor, Processor Type 12 1, 0, EAX, 19:16, model_ext, Extended Model ID 13 1, 0, EAX, 27:20, family_ext, Extended Family ID 15 1, 0, EBX, 7:0, brand, Brand Index 16 1, 0, EBX, 15:8, clflush_size, CLFLUSH line size (value * 8) in bytes 17 1, 0, EBX, 23:16, max_cpu_id, Maxim number of addressable logic cpu in this package [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/ |
H A D | bif_5_0_sh_mask.h | 27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff 28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0 29 #define MM_INDEX__MM_APER_MASK 0x80000000 30 #define MM_INDEX__MM_APER__SHIFT 0x1f 31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff 32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 33 #define MM_DATA__MM_DATA_MASK 0xffffffff 34 #define MM_DATA__MM_DATA__SHIFT 0x0 35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2 36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1 [all …]
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