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/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8127.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
29 MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
30 MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
31 MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
32 MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
33 MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
34 MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
[all …]
H A Dpinctrl-mt8173.c18 #define DRV_BASE 0xb00
21 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
22 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
23 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
24 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
25 MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */
26 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
28 MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */
29 MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */
30 MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */
[all …]
H A Dpinctrl-mt2712.c20 MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
21 MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
22 MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
23 MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
24 MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
25 MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
27 MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
28 MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
29 MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
30 MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
[all …]
H A Dpinctrl-mt6795.c11 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
12 _x_bits, 15, 0)
15 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
16 _x_bits, 16, 0)
19 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
23 PIN_FIELD16(0, 196, 0x0, 0x10, 0, 1),
27 PIN_FIELD16(0, 196, 0x100, 0x10, 0, 1),
31 PIN_FIELD16(0, 196, 0x200, 0x10, 0, 1),
35 PIN_FIELD16(0, 196, 0x400, 0x10, 0, 1),
39 PIN_FIELD16(0, 196, 0x500, 0x10, 0, 1),
[all …]
/openbmc/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]
/openbmc/linux/sound/soc/sof/amd/
H A Dacp-dsp-offset.h15 #define ACP_DMA_CNTL_0 0x00
16 #define ACP_DMA_DSCR_STRT_IDX_0 0x20
17 #define ACP_DMA_DSCR_CNT_0 0x40
18 #define ACP_DMA_PRIO_0 0x60
19 #define ACP_DMA_CUR_DSCR_0 0x80
20 #define ACP_DMA_ERR_STS_0 0xC0
21 #define ACP_DMA_DESC_BASE_ADDR 0xE0
22 #define ACP_DMA_DESC_MAX_NUM_DSCR 0xE4
23 #define ACP_DMA_CH_STS 0xE8
24 #define ACP_DMA_CH_GROUP 0xEC
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4/
H A Dsetup-sh7760.c17 UNUSED = 0,
44 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
45 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
46 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
47 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
48 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
49 INTC_VECT(DMAC, 0x6c0),
50 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
51 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
52 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
[all …]
/openbmc/linux/sound/soc/amd/acp/
H A Dchip_offset_byte.h14 #define ACPAXI2AXI_ATU_CTRL 0xC40
15 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0xC20
16 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0xC24
18 #define ACP_PGFSM_CONTROL 0x141C
19 #define ACP_PGFSM_STATUS 0x1420
20 #define ACP_SOFT_RESET 0x1000
21 #define ACP_CONTROL 0x1004
24 (adata->acp_base + adata->rsrc->irq_reg_offset + offset + (ctrl * 0x04))
26 #define ACP_EXTERNAL_INTR_ENB(adata) ACP_EXTERNAL_INTR_REG_ADDR(adata, 0x0, 0x0)
27 #define ACP_EXTERNAL_INTR_CNTL(adata, ctrl) ACP_EXTERNAL_INTR_REG_ADDR(adata, 0x4, ctrl)
[all …]
/openbmc/linux/arch/sh/include/mach-se/mach/
H A Dse.h16 #define PA_ROM 0x00000000 /* EPROM */
17 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
18 #define PA_FROM 0x01000000 /* EPROM */
19 #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
20 #define PA_EXT1 0x04000000
21 #define PA_EXT1_SIZE 0x04000000
22 #define PA_EXT2 0x08000000
23 #define PA_EXT2_SIZE 0x04000000
24 #define PA_SDRAM 0x0c000000
25 #define PA_SDRAM_SIZE 0x04000000
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7343.c24 DEFINE_RES_MEM(0xffe00000, 0x100),
25 DEFINE_RES_IRQ(evt2irq(0xc00)),
30 .id = 0,
44 DEFINE_RES_MEM(0xffe10000, 0x100),
45 DEFINE_RES_IRQ(evt2irq(0xc20)),
64 DEFINE_RES_MEM(0xffe20000, 0x100),
65 DEFINE_RES_IRQ(evt2irq(0xc40)),
84 DEFINE_RES_MEM(0xffe30000, 0x100),
85 DEFINE_RES_IRQ(evt2irq(0xc60)),
99 [0] = {
[all …]
H A Dsetup-sh7723.c30 DEFINE_RES_MEM(0xffe00000, 0x100),
31 DEFINE_RES_IRQ(evt2irq(0xc00)),
36 .id = 0,
51 DEFINE_RES_MEM(0xffe10000, 0x100),
52 DEFINE_RES_IRQ(evt2irq(0xc20)),
72 DEFINE_RES_MEM(0xffe20000, 0x100),
73 DEFINE_RES_IRQ(evt2irq(0xc40)),
92 DEFINE_RES_MEM(0xa4e30000, 0x100),
93 DEFINE_RES_IRQ(evt2irq(0x900)),
112 DEFINE_RES_MEM(0xa4e40000, 0x100),
[all …]
H A Dsetup-sh7722.c30 .addr = 0xffe0000c,
32 .mid_rid = 0x21,
35 .addr = 0xffe00014,
37 .mid_rid = 0x22,
40 .addr = 0xffe1000c,
42 .mid_rid = 0x25,
45 .addr = 0xffe10014,
47 .mid_rid = 0x26,
50 .addr = 0xffe2000c,
52 .mid_rid = 0x29,
[all …]
H A Dsetup-sh7366.c26 DEFINE_RES_MEM(0xffe00000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0xc00)),
32 .id = 0,
41 [0] = {
43 .start = 0x04470000,
44 .end = 0x04470017,
48 .start = evt2irq(0xe00),
49 .end = evt2irq(0xe60),
56 .id = 0, /* "i2c0" clock */
66 [0] = {
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh3/
H A Dsetup-sh7710.c19 UNUSED = 0,
33 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820),
34 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860),
35 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
36 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
37 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920),
38 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960),
39 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
41 INTC_VECT(IPSEC, 0xbe0),
43 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
[all …]
/openbmc/linux/drivers/net/wireless/marvell/mwifiex/
H A Dpcie.h27 #define PCIE_VENDOR_ID_MARVELL (0x11ab)
28 #define PCIE_VENDOR_ID_V2_MARVELL (0x1b4b)
29 #define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30)
30 #define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38)
31 #define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42)
33 #define PCIE8897_A0 0x1100
34 #define PCIE8897_B0 0x1200
35 #define PCIE8997_A0 0x10
36 #define PCIE8997_A1 0x11
37 #define CHIP_VER_PCIEUART 0x3
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dmac_psc.h37 #define PSC_BASE (0x50F31000)
44 * To access a particular set of registers, add 0xn0 to the base
48 #define pIFRbase 0x100
49 #define pIERbase 0x104
55 #define PSC_MYSTERY 0x804
57 #define PSC_CTL_BASE 0xC00
59 #define PSC_SCSI_CTL 0xC00
60 #define PSC_ENETRD_CTL 0xC10
61 #define PSC_ENETWR_CTL 0xC20
62 #define PSC_FDC_CTL 0xC30
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap36xx-omap3430es2plus-clocks.dtsi10 reg = <0xa00>;
12 #address-cells = <0>;
15 #clock-cells = <0>;
19 ti,bit-shift = <0>;
25 reg = <0xa40>;
27 #address-cells = <0>;
30 #clock-cells = <0>;
35 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sm8250-camss.yaml113 port@0:
308 reg = <0 0xac6a000 0 0x2000>,
309 <0 0xac6c000 0 0x2000>,
310 <0 0xac6e000 0 0x1000>,
311 <0 0xac70000 0 0x1000>,
312 <0 0xac72000 0 0x1000>,
313 <0 0xac74000 0 0x1000>,
314 <0 0xacb4000 0 0xd000>,
315 <0 0xacc3000 0 0xd000>,
316 <0 0xacd9000 0 0x2200>,
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dscu_ast2600.h17 u32 hwstrap; /* 0x500 */
18 u32 hwstrap_clr; /* 0x504 */
19 u32 hwstrap_protect; /* 0x508 */
23 u32 protection_key; /* 0x000 */
24 u32 chip_id0; /* 0x004 */
25 u32 reserve_0x08; /* 0x008 */
26 u32 reserve_0x0C; /* 0x00C */
27 u32 reserve_0x10; /* 0x010 */
28 u32 chip_id1; /* 0x014 */
29 u32 reserve_0x18; /* 0x018 */
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dotx2_reg.h14 #define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
15 #define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
16 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3)
17 #define RVU_PF_VF_BAR4_ADDR (0x10)
18 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
19 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3)
20 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3)
21 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3)
22 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3)
23 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3)
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_pci.h13 #define PEX_IP_BLK_REV_2_2 0x02080202
14 #define PEX_IP_BLK_REV_2_3 0x02080203
15 #define PEX_IP_BLK_REV_3_0 0x02080300
18 #define FSL_PCI_PBFR 0x44
20 #define FSL_PCIE_CFG_RDY 0x4b0
21 #define FSL_PCIE_V3_CFG_RDY 0x1
22 #define FSL_PROG_IF_AGENT 0x1
24 #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
25 #define PCI_LTSSM_L0 0x16 /* L0 state */
40 u32 potar; /* 0x00 - Address */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
[all …]
/openbmc/qemu/include/hw/pci-host/
H A Dpnv_phb3_regs.h19 #define PBCQ_NEST_IRSN_COMPARE 0x1a
20 #define PBCQ_NEST_IRSN_COMP PPC_BITMASK(0, 18)
21 #define PBCQ_NEST_IRSN_MASK 0x1b
22 #define PBCQ_NEST_LSI_SRC_ID 0x1f
23 #define PBCQ_NEST_LSI_SRC PPC_BITMASK(0, 7)
24 #define PBCQ_NEST_REGS_COUNT 0x46
25 #define PBCQ_NEST_MMIO_BAR0 0x40
26 #define PBCQ_NEST_MMIO_BAR1 0x41
27 #define PBCQ_NEST_PHB_BAR 0x42
28 #define PBCQ_NEST_MMIO_MASK0 0x43
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dgt64120.h21 #define GT_CPU_OFS 0x000
23 #define GT_MULTI_OFS 0x120
26 #define GT_SCS10LD_OFS 0x008
27 #define GT_SCS10HD_OFS 0x010
28 #define GT_SCS32LD_OFS 0x018
29 #define GT_SCS32HD_OFS 0x020
30 #define GT_CS20LD_OFS 0x028
31 #define GT_CS20HD_OFS 0x030
32 #define GT_CS3BOOTLD_OFS 0x038
33 #define GT_CS3BOOTHD_OFS 0x040
[all …]
/openbmc/u-boot/include/
H A Dgt64120.h18 #define GT_CPU_OFS 0x000
20 #define GT_MULTI_OFS 0x120
23 #define GT_SCS10LD_OFS 0x008
24 #define GT_SCS10HD_OFS 0x010
25 #define GT_SCS32LD_OFS 0x018
26 #define GT_SCS32HD_OFS 0x020
27 #define GT_CS20LD_OFS 0x028
28 #define GT_CS20HD_OFS 0x030
29 #define GT_CS3BOOTLD_OFS 0x038
30 #define GT_CS3BOOTHD_OFS 0x040
[all …]

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